Uwe Zschenderlein

Residual stress investigations at TSVs in 3D micro structures by HR-XRD, Raman spectroscopy and fibDAC

In this paper the residual stress in single-crystalline Si around W-filled TSVs was determined experimentally by three methods with high spatial resolution and compared to one another. In contrast to Cu as TSV filler, W has the potential advantage of a lower CTE mismatch to Si resulting in lower thermally induced stress at the TSV-interface. As test layout a cross-sectioned double-die stack was used consisting of a top die with TSVs which is bonded by Cu-Sn Solid Liquid Interdiffusion Bonding (SLID) to the bottom die. Three different experimental methods have been used to determine mechanical stresses in silicon nearby tungsten TSVs - HR-XRD performed at a synchrotron beamline, microRaman spectroscopy and stress relief techniques put into effect by FIB milling. All methods possess, to a different extend, high spatial resolution capabilities. However they differ in their sensitivity and response to the particular stress tensor components relevant for the residual stress state nearby TSV structures. Stress measurements were performed on test samples with W-TSVs in thinned dies, which were SLID bonded to a thicker Si substrate die. The measurements captured stresses introduced by the W-TSV as well as by the wafer bonding process. A stress range from several MPa to hundreds of MPa could have been covered with a spatial resolution ranging from 100 nm to tens of microns. Measurement results were compared to one another and to simulated stresses from finite element analysis (FEA). All experimental methods show the influence of W and Cu-Sn-Bond in Si. The very high stress sensitivity for HR-XRD below 1 MPa could be shown. For small stress gradients the analysis of the peak position gives reasonable results and for larger stress gradients a profile analysis of the diffraction peak is more accurate. The results show that in intrinsic stress in W may have to be considered in FEA and more attention should be directed to the accuracy of the FE-modelled Cu-Sn SLID bond with respect to shrinkage during phase formation of Cu3Sn.

All-Copper Flip Chip Interconnects by Pressureless and Low Temperature Nanoparticle Sintering

Flip chip interconnects purely made out of Cu, so-called all-Cu interconnects, have the potential to overcome the present current capacity limit of state-of-the-art solder based interconnects, while meeting the demand for ever decreasing interconnect pitches. Parasitic effects in solder based interconnects, caused by interdiffusion of various metals, are mitigated in all-Cu interconnects. In this work, all-Cu interconnects were formed by the use of low temperature and pressureless sintering of Cu nanoparticles. Thereby, a Cu paste material was applied between the Cu pillars of a silicon chip and the Cu pads on a silicon substrate by a dip transfer method. The electrical and mechanical properties of sintered Cu were characterized on films of the same Cu pastes. The porous films resulted in 4.4 times higher electrical resistivity and one order of magnitude reduced mechanical stiffness and tensile strength compared to bulk Cu. All-Cu interconnects with a diameter of 30 μm and a pitch of 100 μm were formed with an optimized Cu particle distribution and sintering procedure. Resistances down to 1.7 ± 0.5 mO were measured for these all-Cu interconnects which is comparable to solder based benchmark interconnects. However, the porosity of the sintered Cu interconnect results in lower shear strength compared to the solder benchmark.

Review of percolating and neck-based underfills with thermal conductivities up to 3 W/m-K

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-ofthe-art capillary thermal underfill (0.7 W/m-K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry vs. wet filling of filler particles, the optimal bi-modal nanosuspension formulation and matrix material feed, and the overpressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 500 thermal cycles. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-art capillary thermal underfill.

Embedded power insert enabling dual-side cooling of microprocessors

A dual-side cooling topology is proposed that is achieved by embedding a power insert into the organic substrate of a chip or chip stack. The power insert consists of vertical copper lamellas supporting lateral current feed in addition to vertical heat dissipation at minimal electrical and thermal gradients. The lateral current feed capability is key to enable the introduction of the cold plate on the bottom side of the substrate. Thermal and electrical finite-element modeling was performed to determine the optimal pitch of the power insert lamella of 270 μm and 350 μm to obtain a total thermal resistance of 21 K-mm2/W and a voltage drop of 2 mV, respectively. The 10 × 10 mm2 power inserts are fabrication by means of a copper and prepreg lamination process, followed by a sawing and polishing singulation step. The embedding of the power insert is described, considering additional redistribution layers to accommodate also smaller interconnect pitches on the chip side. The effective thermal conductivity of the power insert was derived by bulk-thermal measurement and yielded 320±50 W/m-K, ten times the performance of state-of-the-art substrates with thermal via arrays. Finally, we demonstrate the benefits of the dual-side cooling approach in a thermal benchmark study that compares it with back- and front-side cooling. Dual-side cooling not only halfs the total thermal resistance, but also enables the integration of pyramid-like chip stacks and the placement of high-power dies in the bottom tiers of a stack.

Application of Energy Dispersive X-Ray Diffraction for the Efficient Investigation of Internal Stresses in Thin Films

Internal stresses are very important for the performance of protective hard coatings. Tensile stresses favour the formation and propagation of cracks, inducing fracture and corrosion. Medium compressive stresses hinder fatigue. But high compressive stresses, typically for hard coatings produced by PVD (physical vapour deposition) processes, support delamination in order to relax the stored elastic energy. However notwithstanding its relevance, the internal stresses are only seldom used for the optimisation and quality control of hard coatings in industry. This unsatisfying situation is caused by the deficit in efficient measuring methods. The results of thin sheets, where the stresses can be simply measured by their curvature, are not necessarily representative for the coating of thicker parts. The conventional XRD (X-ray Diffraction), based on angle-dispersive evaluation needs expensive devices and is rather time consuming. The energy-dispersive technique opens new possibilities. It is based on polychromatic radiation. The interference of the lattice plane reflections corresponding to the Bragg-equation is investigated by the diffraction intensity of the different wavelength (or photon energies), not by varying the Bragg-angle as in conventional XRD. Hence, the whole diffraction pattern can be obtained in one shoot without the use of any goniometer. This allows the construction of small and compact measuring devices and the reduction of measuring time to a few minutes. The capability of the ED-XRD (Energy Dispersive X-ray Diffraction) is demonstrated for titanium nitride and chromium nitride films deposited by cathodic vacuum arc with varying parameters. Comparisons were made with the much more time-consuming AD-XRD (Angle Dispersive X-ray Diffraction) for residual stress analysis. The results of both methods are in good agreement.

Reliability experiments of sintered silver based interconnections by accelerated isothermal bending tests

Abstract Integration of more functionality and smaller chips into decreasing package volume leads to increasing heat generation. In addition, the use of new compound semiconductors like SiC and GaN require a high thermal conductivity of the interconnect materials. One of the promising solutions is a layer of sintered silver between semiconductor and substrate. The advantages compared to conventional solders are significant. A higher thermal and electrical conductivity in combination with a higher duty temperature due to a higher melting point should enhance the reliability of the package. However, even as the large scale commercial usage of the material has been started by the industry recently, many important details of the mechanical properties and the reliability behavior are still unknown. While the thermal properties could be characterized relatively easy and are quite repeatable and stable, the mechanical properties - important for the reliability - are extremely process-dependent and wide-spreading. The hunt for lowest feasible sintering process parameters - such as temperature, time and especially pressure - even amplify that behavior and led to an impasse in some cases. Also their failure mechanisms, to be identified in lifetime investigations, are yet unknown as well as their stability and predictability. In order to enable prolonged function of these interfaces, thermo-mechanical reliability has to be assured. Within this paper, we show the status of silver sintering and the problems regarding mechanical material characterization found in literature. Additionally, we present a guideline for the mechanical acceleration of reliability experiments by isothermal bending tests. Finally a proof of concept by failure analysis will be presented.

Monte Carlo simulation of X-ray diffraction embedded in experimental determination of residual stresses in microsystems

In this paper a simulation is presented which tracks photons through complex material systems. Besides the usual Compton and Rayleigh scattering that is covered in high energy radiography simulations the presented model considers Bragg-Laue diffraction. The implementation bases on a Monte Carlo code to account for the scattering during radiography. In this paper first results of the simulation are presented. A simple radiation as well as a diffraction experiment was setup. The attenuation coefficient and the position of the diffraction peaks drawn out of the simulation were in good agreement with the literature.