V. Baena-Lecuyer

DVB-T2: The Second Generation of Terrestrial Digital Video Broadcasting System

This paper provides a review of the second generation of terrestrial digital video broadcasting standard (DVB-T2). DVB-T2 is the evolution of DVB-T and, together with DVB-S2 and DVB-C2, inaugurated a new transition from the first-generation digital broadcasting systems, similar to the transition from analog-to-digital systems. In this paper, the most relevant features of DVB-T2 are explained in detail, along with their benefits and trade-offs. This paper also presents a comprehensive review of the laboratory and field trial results available so far. Especial emphasis is placed in the results of the measurements carried out to test the mobile reception and the novel technologies as multiple input single output and time frequency slicing.

Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems

Abstract Modern trends in technology require efficient control and processing platforms based on connected software-hardware subsystems. Due to their complexity and size, algorithms implemented on these platforms are difficult to test and verify. When these types of solution are being designed, it is necessary to provide information of the internal values of registers and memories of both the software and hardware during the execution of the complete system. The final architecture of the targeted design and its debugging capabilities strongly depends on how the hybrid system is connected and clocked. This article discusses different architectural strategies that have been adopted for a hybrid hardware-software platform, built ready for debugging, and that uses components that can be easily found with a few special features. All the solutions have been implemented and evaluated using the UNSHADES-2 framework.

Simplified Rotated Constellation Demapper for Second Generation Terrestrial Digital Video Broadcasting

The constellation rotation and cyclic Q-delay technique has been adopted in second generation terrestrial digital video broadcasting to provide signal space diversity, improving the system performance under severe multipath propagation environments. The main drawback of this technique is the hardware complexity introduced in the demapping process compared to non-rotated constellations. In this brief, we present a simplified demapper that reduces up to 78% the number of required operations with almost no performance degradation compared to the results of the ideal max-log demapper.

Cubic Metric Reduction for DCO-OFDM Visible Light Communication Systems

Visible light communication (VLC) systems with a direct current-biased optical orthogonal frequency division multiplexing (DCO-OFDM) architecture suffers from the well-known problem of high peak-to-average power ratio (PAPR). A DCOOFDM signal at the input of the light emitting diode (LED) with high PAPR can experience clipping due to its limited dynamic-range. This causes distortion and degradation of the signal quality, forcing a large power back-off, and so leading to an inefficient use of the LEDs. In order to resolve this problem, we propose to apply a power derating reduction technique at the VLC transmitter based on a modification of the active constellation extension (ACE) method with two important changes: a better predictor of the power derating than the PAPR, the cubic metric (CM), and a more effective clipping stage. With the proposed method, we achieve a significant CM reduction as large as 7.1 dB, which contributes to a noticeable gain in the input power back-off of 2.5 dB or an important reduction of signal distortion, and a greater illumination to communication efficiency (ICE), higher than 30%.

Multi-carrier Receiver for Broadband Power Line Communications

This paper presents the design of a broadband power line communication (BPLC) receiver optimized for reduced hardware complexity. To this end, the Radio-Frequency (RF) stage uses a direct conversion architecture while some innovative solutions are used in the base-band signal processing, such as a new frequency offset synchronization scheme based on the frequency domain. Every part of the receiver has been optimized using a new non-commercial hardware-software co-simulation package named BROCOLI (Broadband Co-simulation Library) based on a set of hierarchical models, specially developed for this application. A prototype of the BPLC transceiver has been built and some experimental results are shown which validate the design process and the implemented solutions.

Design of an efficient CORDIC-based architecture for synchronization in OFDM

This paper presents a new architecture to estimate the time and frequency offsets required to synchronize packed-based orthogonal frequency division multiplexing (OFDM) modulation receivers. The proposed estimators, which operate in the frequency-domain, use CORDIC (coordinate rotation digital computer) processors to achieve an efficient hardware implementation which is simpler than other computational intensive estimators based on processing in the time-domain. The hardware saving is twofold: the proposed implementation does not require complex cells such as multipliers or dividers; and some cells already existing in OFDM receivers for pay-load demodulation are reused during the synchronization phase. In addition, this paper also shows how to optimize the CORDIC cells, in terms of number of iterations, to provide a given signal-to-noise ratio (SNR) due to approximation error, and proposes an error propagation model for the proposed synchronization architecture

Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability

Modern FPGAs use SRAM-cells to store the programming bits that drive the switching matrices. The area of these SRAM cells can be as large as 40% of the total area. This figure dramatically increases in the case of multicontext FPGAs, where the programming configuration has to be repeated as many times as contexts. This problem is alleviated if the switches that connect an input line to several output lines in each switching block are driven by a decoder. In this case, the number of SRAM cells decreases in O(log), at the cost of routability. This paper shows with experimental results obtained from 175 benchmark circuits that, for usual FPGA parameters, routability losses are small, making the decoder-driven switch (DDS) approach an excellent method for reducing FPGA area by as much as 20%, while preserving routability.

Simplified Detection for DVB-NGH MIMO Decoders

Nowadays, communication systems need to satisfy very demanding constraints in order to cope with users new necessities. One of the most promising techniques to improve the system capacity is multiple input multiple output (MIMO). However, the use of MIMO implies a huge complexity increase in the detection process. In this paper, a method to reduce the aforementioned complexity is presented. Although the proposed method is analyzed for digital video broadcasting next generation for handhelds, its implementation is useful for any MIMO system that requires the computation of log likelihood ratios (LLRs), used by the low density parity check codes. The presented technique consists of applying a simplification when calculating the Euclidean distances needed by the LLRs. The simplification avoids almost all the multiplications, very area demanding when translated into hardware, and presents a performance loss under 0.1 dB.

A new method for simultaneous fine time synchronization and frequency offset estimation in OFDM with simple hardware

The paper presents a new method to provide simultaneous time and frequency offset estimation that operates in the frequency domain by analyzing the modulus and angle of a synchronization symbol. When compared to those estimators based on computational intensive time-correlations, the main advantage of the proposed estimator is in the hardware implementation. In the proposed method, no additional hardware is required, as the already existing FFT processor and the polar coordinates translator (typically a CORDIC processor) used for OFDM normal operation are reused in the synchronization phase. Simulation results are presented using different conditions and channel models showing a negligible decrease in performance when compared to other methods.

RAISE: a detailed routing algorithm for SRAM based field-programmable gate arrays using multiplexed switches

This paper describes a new detailed routing algorithm, specially designed for those architectures that are found in most recent generations of Field-Programmable Gate Arrays (FPGAs). The algorithm also brings a solution for those architectures where multiplexed switches are used in order to decrease the chip area like the recently proposed FIPSOC FPGA. The algorithm, called RAISE, can be applied to a broad range of optimization problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels, with or without the use of multiplexed switches. RAISE (Router using Adaptive Simulated Evolution) searches not just for a possible solution, but tries to find the one with minimum delay. Excellent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.