A. Torralba

Speed control of induction motors using a novel fuzzy sliding-mode structure

This paper presents a new approach to indirect vector control of induction motors. Two nonlinear controllers, one of sliding mode type and the other PI-fuzzy logic-based, define a new control structure. Both controllers are combined by means of an expert system based on Takagi-Sugeno fuzzy reasoning. The sliding-mode controller acts mainly in a transient state while the PI-like fuzzy controller acts in the steady state. The new structure embodies the advantages that both nonlinear controllers offer: sliding-mode controllers increasing system stability limits, and PI-like fuzzy logic based controllers reducing the chattering in permanent state. The scheme has been implemented and experimentally validated.

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistors threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.

A continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to interferers

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional /spl Sigma//spl Delta/ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm/sup 2/ in a 0.18-/spl mu/m digital CMOS technology.

A new family of very low-voltage analog circuits based on quasi-floating-gate transistors

A new family of very low-voltage analog circuits is introduced. These circuits do not show the GB degradation that characterizes other low-voltage approaches based on floating-gate transistors. The proposed approach is validated with experimental results of a CMOS mixer in 0.5-/spl mu/m CMOS technology with 0.7-V input signal swing that operates on a single 0.8-V supply with transistor threshold voltages of 0.67 V.

FASY: a fuzzy-logic based tool for analog synthesis

A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy-logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two-phase optimizer sizes all elements to satisfy the performance constraints minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies.

A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range

A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8-/spl mu/m CMOS process. Experimental results show a frequency tuning range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption.

Low-voltage CMOS operational amplifiers with wide input-output swing based on a novel scheme

A scheme to achieve low-voltage wide-bandwidth operation of CMOS op amps with rail-to-rail input and output swing and constant gm is presented. It is based on a novel concept that uses a floating voltage controlled voltage source in the feedback path of the op amp in order to keep its input terminals close to one of the supply rails. Postlayout simulations on a 1.2 V rail-to-rail op amp with 13 MHz GB are presented which verify the proposed scheme.

ASIC implementation of a digital tachometer with high precision in a wide speed range

A common method in adjustable speed drives uses an incremental shaft encoder and an electronic circuit for velocity estimation. The usual method of counting pulses coming from the encoder in a fixed period of time produces a high-precision velocity estimate in the high-speed range. High precision in the low-speed range can be achieved measuring the elapsed time between two successive pulses coming from the encoder. In this paper, a mixed method that combines the best of the two previously mentioned approaches has been implemented using a simple electronic circuit based on one field-programmable gate array (FPGA) and one read-only memory (ROM).

A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors

A new class AB differential stage that operates with a single supply voltage of less than two transistor threshold voltages is introduced. This circuit has utilization in high slew rate one stage op amps, two stage op amps with class AB input and output stages and linear transconductors. The circuit was verified with simulations and experimentally. It it is shown to have lower voltage supply requirements than other commonly used structures reported in literature.

New Continuous-Time Multibit Sigma–Delta Modulators With Low Sensitivity to Clock Jitter

In this paper, new continuous-time sigma-delta modulators (SDMs) are proposed where the output of a multibit (MB) quantizer is digitally converted to a single-bit pulsewidth-modulated (PWM) signal at a higher rate. The PWM signal is then fed back to the input through a finite-impulse-response digital-to-analog converter (DAC). The proposed modulators are shown to be less sensitive to clock jitter than their equivalent MB SDM, while their amplifiers have similar speed and power requirements. Furthermore, the proposed modulators do not require dynamic-element-matching techniques in the feedback path because a mismatch of the unit elements in the MB DAC does not produce distortion nor increases the noise floor in the signal band.