S.V. Polonsky

Transmission of single-flux-quantum pulses along superconducting microstrip lines

The authors analyzed, designed, and tested drivers and receivers which make it possible to connect distant circuits of the rapid single-flux-quantum (RSFQ) logic/memory family by passive superconducting microstrip lines. Using these circuits implemented with a niobium trilayer fabrication technology, reliable transmission and reception of the SFQ pulses over distances up to 1 cm, with margins of bias currents as wide as +or-30%, have been demonstrated. The pulses can be passed along wide lines (20 mu m for 3.5 mu Nb-Al/sub 2/O/sub 3/-Nb Josephson junction technology) over such distances and can be picked up by the RSFQ receiver.<<ETX>>

PSCAN'96: new software for simulation and optimization of complex RSFQ circuits

The first version of PSCAN program (Personal Superconductor Circuit ANalyzer) was introduced in 1991. The program is a general purpose superconductor circuit simulator with an emphasis on the design of Rapid Single-Flux-Quantum (RSFQ) circuits. In the intervening years a number of new features were gradually added to the program. In particular, verification of the correct circuit behavior was enhanced using a special hierarchical Single-Flux-Quantum Hardware Description Language (SFQHDL). Next, a fast heuristic algorithm for margin optimization was introduced, which increased the number of parameters that can be simultaneously optimized in reasonable CPU times. Finally, recently we improved the numerical algorithm used for the simulation by using sparse symmetric positive definite matrices (instead of general structure band matrices as before). As a result, simulation speed has increased almost tenfold. Now it takes about 30 seconds of a CPU time on HP716/100 workstation to run a 2000 ps simulation of a 120-Josephson-junction circuit, and about a week to optimize all parameters of a two hundred Josephson junction circuit. We have merged all these improvements in a new version of our simulator, PSCAN96.

Rapid single flux quantum random access memory

A new design concept for the Josephson-junction random access memory (RAM) has been developed. In contrast to previous RAMs based on single flux quantization (SFQ), in our system READ and WRITE operations employ ballistic transfer of SFQ pulses along bit lines (either Josephson transmission lines, or passive superconducting microstrip lines, or their combination). The basic memory cells are the single-junction SQUIDs, connected serially by the bit lines and inductively coupled to word lines. READ and WRITE operations are performed by sending SFQ pulses in appropriate directions along bit lines, and DC currents of appropriate polarity into word lines. This approach allows design of very dense memories with n/spl les/2 Josephson junctions per bit, memory cell area smaller than 80 /spl lambda//sup 2/ (where /spl lambda/ is the minimum feature size), and the critical parameter margin well above /spl plusmn/20%. In this paper we present the general structure of the RSFQ RAM, as well as design and results of testing of the basic memory cell and decoder circuitry using Hypres 3.5-/spl mu/m, 1-kA/cm/sup 2/ Nb-trilayer technology.<<ETX>>

Broadband interfacing of superconducting digital systems to room temperature electronics

We have developed and tested simple and inexpensive electronics for interfacing Rapid Single-Flux-Quantum (RSFQ) Josephson-junction circuits to room temperature digital systems. Voltage-level (Non-Return-to-Zero) bit signals with a swing of /spl sim/150 uV, developed on-chip by standard SFQ/DC converters, and in some cases amplified to 1.5 mV swing by HUFFLE-type circuits, are passed to the 300 K environment using a high density (40 channel) flexible coplanar waveguide assembly. AC-coupled, 2-3 stage microwave Si-bipolar amps, and Emitter-Coupled-Logic (ECL) buffers accomplish voltage level translation to the standard ECL levels, Using this technique, data rates in excess of 1 Gb/s per channel can be achieved at low cost per channel,.<<ETX>>

RSFQ arithmetic blocks for DSP applications

We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.<<ETX>>

Delay insensitive RSFQ circuits with zero static power dissipation

Total power dissipation in RSFQ circuits consists of two parts, dynamic and static. Dynamic power is dissipated in Josephson junctions performing useful logical and data transmission operations. This dissipation is fundamental and proportional to the data rate (at 4 K, of the order of 10/sup -18/ Joule per bit). Static power is dissipated in resistors used by RSFQ circuits to distribute dc bias current between Josephson junctions. This part of dissipation is not intrinsic to RSFQ circuits and in principle can be eliminated. The goal of this work is to show that Delay Insensitive (DI) RSFQ primitives can be modified so that resistors are no longer required in the dc power supply distribution network, so that the on-chip static power dissipation is absent. In this report we present the schematics for such primitives, define the class of circuits that allow resistor-free current distribution network, and formulate the requirements to the design of this network.

Towards broadband communications between RSFQ chips

We have investigated the applicability of Single Flux Quantum (SFQ) and Multiple Flux Quanta (MFQ) approaches to communications between RSFQ logic/memory chips. SFQ pulses can be transmitted between chips if inductive discontinuity L lies below 3-5 pH. For larger L one can employ MFQ pulses which have the same width as the SFQ pulses, but M times larger amplitude. For example, for L=20 pH, M=4 is sufficient. We have developed an MFQ driver and a receiver capable of transmitting the data in 10-20 Gbps/pin range for the use in simple flip-chip MCM packages based on Si substrates.

Modulation and demodulation of 2 GHz pseudo random binary sequence using SFQ digital circuits

The high speed and low power needed for Spread Spectrum communications leads to a desirable application of digital superconductivity. Low temperature Nb/AlOx/Nb digital Single Flux Quantum (SFQ) circuits have been designed and fabricated in our facility, which compose critical subcircuits of the superconductive Spread Spectrum Modem. Four- and 6-bit Pseudo Random Binary Sequence (PRES) generators with output latching amplifiers have been produced and operated at up to 5.4 GHz. On chip modulation and de-modulation of these PRES codes have been performed with time resolution of less than one chip of the code. High-speed off-chip data was XORed with the on-chip PRES at up to 3.7 GHz to produce the modulated pattern. Rapid synchronization allows the code to start within one clock cycle of being fully reset, and the latching output amplifier gives enough power to do real time room temperature measurements of high-speed SFQ circuits.

Bit error rate measurements for GHz code generator circuits

A new method of analyzing bit error rates (BERs) for SFQ circuits and their outputs at GHz speeds will be presented. This method was used to test four- and six-bit pseudorandom code generators. The code generators were operated in free-run mode, i.e., without a synchronization (Reset) pulse. This enabled us to conduct BER testing to much lower levels than when the code generator is operated in Reset mode. The SFQ circuit output was amplified with a superconducting output latch to give voltage levels suitable for display on a sampling scope. The GHz output data was analyzed by external computer software; this permitted extended tests without user supervision. With the code generators operating in free-run mode, they routinely gave bit error rates (BERs) in the 10/sup -11/ range; the best BER recorded was 1.1*10/sup -13/ (2 errors in /spl sim/2.5 hours) at 2 GHz. We have successfully tested these code generators at frequencies in excess of 3.5 GHz with BERs in the 10/sup -10/ range as well.

Spread spectrum data transfer from dewar to dewar at 2 gigachips per second

Spread spectrum data modulation, transmission, and demodulation has been demonstrated between SFQ chips in separate dewars. The baseband demonstration consisted of modulating (encoding) data with a spreading code, transmitting the coded data to a Receiver and demodulating (decoding) the data using an identical spreading code. The Transmitter code was produced by a 2 GHz, 4-bit SFQ pseudorandom sequence generator creating a 15-chip spreading code, which modulated a /spl sim/133 MHz data source. This data was output by a 10/spl times/ superconducting latch providing /spl sim/8 mV of AC drive. This signal was fed through 50-/spl Omega/ coaxial cable to a SFQ Receiver chip in a separate dewar. No amplification of the AC signal between the dewars was needed, however, a slight DC bias was added to the signal as a flux bias for the input SQUID on the Receiver. The Receiver chip consisted of an identical SFQ pseudorandom sequence generator and a data demodulation gate. Demodulating the received data with the code generator produced a replica of the data signal in RZ form. Both time forward and time reversed codes for the spreading/despreading sequence were created.