V. Speziali

Suboptimal filtering of 1/ƒ-noise in detector charge measurements☆

Processing of 1tf-noise by suboptimal filters in detector charge measurements is considered. The achievable values of equivalent noise charge are compared to those provided by the optimum filter. Some aspects of filters processing 1tf-noise, like the degradation in the accuracy of charge measurements due to a bipolar or to a unipolar, flat-topped weighting function are described. Several conclusions are expected to be useful in the design of analog processors for radiation detectors when the front-end 1tf-noise is not negligible.

Submicron CMOS technologies for low-noise analog front-end circuits

This paper presents a study of the noise behavior of submicron CMOS transistors, in view of applications to high-density mixed-signal front-end systems for high-granularity detectors. The goal of this work is extending the knowledge in this field, presently focused on 0.25 /spl mu/m processes, to the following generation of CMOS technologies (with 0.18 /spl mu/m minimum gate length). The white component of the noise voltage spectrum, which is most important for fast signal processing, and the 1/f noise contribution are experimentally characterized with noise measurements in a wide frequency range. The results of this analysis are used to establish low-noise design criteria concerning the choice of the polarity and of the channel dimensions (length and width) of the preamplifier input device in low-power operating conditions. A comparison with similar noise measurements on CMOS devices belonging to a 0.35 /spl mu/m process allows estimating the impact of gate-length scaling on both white and 1/f noise components. The noise radiation tolerance is also a key parameter for many front-end systems. It was evaluated by exposing the devices to high doses of ionizing radiation.

Comparison of ionizing radiation effects in 0.18 and 0.25 /spl mu/m CMOS technologies for analog applications

We present a comparative study of ionizing radiation effects in 0.18 and 0.25 /spl mu/m CMOS transistors, with the goal of evaluating the impact of device scaling in the design of low-noise rad-hard analog circuits. Device parameters were monitored before and after irradiation with 10 keV X-rays and /sup 60/Co /spl gamma/-rays and after subsequent annealing. The effects of different biasing conditions during irradiation and annealing are discussed. The results are used to point out the different radiation hardness properties of the examined technologies, belonging to different CMOS generations.

Instrumentation for noise measurements on CMOS transistors for fast detector preamplifiers

High-density, high-speed CMOS and BiCMOS technologies are today widely used for the design of readout integrated circuits for room temperature X and /spl gamma/-ray imaging detectors. This paper describes a laboratory instrument that was developed to characterize the noise performances of CMOS devices to be used for high speed analog signal processing. These instruments extend the noise measuring capabilities beyond 100 MHz to detect the white noise component beyond the 1/f noise corner frequency, which in shorter channel devices shifts to higher values as compared to long-channel transistors.

Experimental study and modeling of the white noise sources in submicron Pand N-MOSFETs

This paper presents the results of the experimental characterization of the channel thermal noise in MOSFETs belonging to a submicron gate process, with minimum gate length L=0.35 /spl mu/m. The data are compared with a noise model taking into account short-channel effects such as velocity saturation and hot carriers. The contribution of gate and substrate parasitic resistors is also evaluated and included in the model. The analysis is carried out for devices with various gate geometries, investigating the behavior of the noise-related parameters in the range of small gate-to-source overdrive voltages, which is of major concern for low-power circuits.

Resolution Limits in 130 nm and 90 nm CMOS Technologies for Analog Front-End Applications

In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology generation, to implement readout integrated circuits for future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on two CMOS commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Deep-submicron complementary MOS processes have made the development of ASICs for HEP instrumentation possible. In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

Low noise front-end electronics for microstrip position sensors and vertex detectors for experiments at TeV energies

Abstract A low noise front-end system suitable for signal acquisition from a microstrip detector has been developed. The system is specifically intended for experiments with beams of high intensity and it is able to operate with noise weighting functions as short as 200 ns and detector capacitances up to 50 pF, yet preserving outstanding noise performances. As a first application, the front-end system described here is going to be employed in the vertex detector of the E687 experiment, due to be performed at the Fermilab Tevatron.