Lodovico Ratti

Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime

Degradation mechanisms associated to lateral isolation oxides are discussed to account for total ionizing dose effects on the noise performance of 90 nm and 130 nm CMOS devices and for their dependence on geometry and operating conditions. In NMOSFETs with a conventional open layout, after irradiation the parasitic transistor at the device edges turns on and contributes to the total device noise. The paper provides a model to help understanding the impact of this radiation-induced noise contribution on white and 1/f noise terms. The different behavior of NMOSFETs in the two examined technology nodes is analyzed in this framework, and design criteria to reduce noise degradation in irradiated devices are discussed.

Radiation hardness perspectives for the design of analog detector readout circuits in the 0.18-/spl mu/m CMOS generation

This paper presents a study of the ionizing radiation tolerance of analog parameters of 0.18-/spl mu/m CMOS transistors, in view of the application to the design of front-end integrated circuits for detectors in high-energy physics experiments. Static, signal, and noise performances of devices with various gate dimensions were monitored before and after irradiation up to a 300-kGy(Si) total dose of /sup 60/Co /spl gamma/-rays. Different device biasing conditions under irradiation were used, and the relevant results are discussed. A comparison with previous CMOS generations is carried out to evaluate the impact of device scaling on the radiation sensitivity.

Total ionizing dose effects on the noise performances of a 0.13 /spl mu/m CMOS technology

This paper presents a study of the ionizing radiation tolerance of 0.13 /spl mu/m CMOS transistors, in view of the application to the design of rad-hard analog integrated circuits. Static, signal and noise parameters of the devices were monitored before and after irradiation with /sup 60/Co /spl gamma/-rays at a 10 Mrad total ionizing dose. The effects on key parameters such as threshold voltage shift and 1/f noise are studied and compared with the behavior under irradiation of devices in previous CMOS generations.

Continuous Time-Charge Amplification and Shaping in CMOS Monolithic Sensors for Particle Tracking

In this paper, the use of continuous time charge amplification and shaping is proposed for processing the signal delivered by CMOS pixel sensors in charged particle tracking applications. Such a choice aims at exploiting the large scale of integration of modern deep submicron CMOS technologies to incorporate into the design of a single device both the potential for thin detector fabrication, inherent in the concept of monolithic active pixel sensors (MAPS), and the data sparsification capabilities featured by hybrid pixels. With respect to classical MAPS, adoption of the above readout method involves a substantial change in the guidelines for the design of the front-end electronics and of the whole elementary cell, in order not to jeopardize the collection efficiency of the sensitive electrode. For the purpose of supporting the feasibility of the proposed solution, the paper discusses some experimental data and simulation results relevant to monolithic CMOS sensor prototypes, fabricated in a 0.13 mum technology, which were designed according to the mentioned rules. Finally, the performances of an all NMOSFET charge preamplifier, suitable for improving charge collection efficiency, are investigated through circuit simulations

FSSR2, a self-triggered low noise readout chip for silicon strip detectors

The FSSR2 is the second release of the Fermilab Silicon Strip Readout Chip. The chip has been designed and fabricated in a 0.25 mum CMOS technology for high radiation tolerance. The first release, simply called the FSSR, was a prototype version with many different analog front-end configurations. The best solution was chosen for the FSSR2 chip to optimize the noise, according to criteria discussed in this paper. The FSSR2 has been designed for the silicon strip detectors of the BTeV experiment. The chip services 128 strips and provides address, time and magnitude information for all hits. Several programmable features are included in FSSR2, such as an internal pulser, a baseline restorer and a signal peaking time selectable among four values in the range between 65 ns and 125 ns. The circuit design and the performance of FSSR2 are discussed in this paper

Design Optimization of Charge Preamplifiers With CMOS Processes in the 100 nm Gate Length Regime

Low noise design of charge sensitive amplifiers in deep submicron CMOS technologies is discussed based on the experimental characterization of transistors belonging to a 130 nm and a 90 nm minimum channel length processes. After briefly examining the main preamplifier noise sources, residing in the input element, achievable resolution limits in charge measuring systems employing such technologies are discussed under different detector capacitance, processing time and power dissipation constraints. The equivalent noise charge (ENC) model adopted in this work takes into account the behavior of series 1/f noise as a function of the overdrive voltage in PMOS devices. Moreover, noise in the gate current, whose effects could be neglected in past CMOS technologies featuring larger gate oxide thickness, is shown to play a role in the optimization process, significantly affecting the preamplifier performance at long shaping times. The extent of this contribution, besides depending on the drain current in the input device, is also determined by its drain voltage, which therefore may become a critical parameter in the design of low noise analog blocks.

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Noise Characterization of 130 nm and 90 nm CMOS Technologies for Analog Front-end Electronics

Deep-submicron complementary MOS processes have made the development of ASICs for HEP instrumentation possible. In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25, and 0.18 mum technologies from different foundries. This allows us to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicrometer CMOS processes

Integrated front-end electronics in a detector compatible process: source-follower and charge-sensitive preamplifier configurations

This study is concerned with the simulation and design of low-noise front-end electronics monolithically integrated on the same high-resistivity substrate as multielectrode silicon detectors, in a process made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST) of Trento, Italy. The integrated front-end solutions described in this paper use N-channel JFETs as basic elements. The first one is based upon an all-NJFET charge preamplifier designed to match detector capacitances of a few picofarads and available in both a resistive and a non resistive feedback configuration. In the second solution, a single NJFET in the source-follower configuration is connected to the detector, while its source is wired to an external readout channel through an integrated capacitor.