V. V. Saposhnikov

A New Design Method for Self-Checking Unidirectional Combinational Circuits

In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters. Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs. The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods. The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code. All single stuck-at faults are detected by the method proposed.

New self-checking circuits by use of Berger-codes

In this paper a new approach for concurrent checking by Berger codes is proposed. We modify a subset of outputs of the original circuit by adding modulo 2 the outputs of a complementary circuit. In the error free case the unmodified outputs together with their corresponding modified outputs are elements of a Berger code. The number of outputs of the original circuit does not increase. Compared to the traditional method of concurrent checking by Berger codes, a smaller checker is needed.

Self-Checking Combinational Circuits with Unidirectionally Independent Outputs

In this paper we propose a structure dependent method for the systematic design of a self-checking circuit which is well adapted to the fault model of single gate faults and which can be used in test mode.

Self-dual parity checking-A new method for on-line testing

Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a self-dual complement of a given Boolean function. The parity prediction function f/sub p/ of ordinary parity checking is replaced by the self-dual complement /spl delta//sub p/ of this function such that the module-2 sum of the outputs of the monitored circuit and of /spl delta//sub p/ is an arbitrary self-dual Boolean function h. Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement /spl delta//sub p/ is small. Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs. The fault coverage of this method is almost the same as for parity checking. The usefulness of the proposed method is demonstrated for MCNC benchmark circuits.

A new method for concurrent checking by use of a 1-out-of-4 code

In this paper a new method for concurrent checking is proposed. For an arbitrarily given combinational circuit f an additional complementary circuit g is determined such that for every input the componentwise modulo 2 sum of the corresponding outputs of f and g is an element of a considered cone as long as no error occurs. The new method of concurrent checking is developed for the concrete case of 1-out-of-4 codes.

Self-dual duplication for error detection

In this paper we propose a new method for the implementation of a self-dual circuit with alternating inputs. For every circuit output the self-dual complement is designed. Contrary to ordinary duplication and comparison the corresponding self-dual complements and the monitored circuit itself can be jointly, implemented. The self-dual duplicated circuits can be used in test mode, online mode and in fast mode without alternating inputs. Because of the necessary time redundancy, the approach is especially useful for online testing of control systems for which time is not critical.

Necessary and sufficient conditions for the existence of totally self-checking circuits

In this paper, concurrent checking by use of a complementary circuit for an 1-out-of-n code is investigated. For an arbitrarily given combinational circuit, necessary and sufficient conditions for the existence of a totally self-checking checker are derived for the first time.

New Self-dual Circuits for Error Detection and Testing

In this paper new methods for the transformation of a given combinational circuit into a self-dual circuit based on the notion of a self-dual complement are investigated. The large variety of self-dual complements can be utilized to optimize the transformed self-dual circuit. Self-dual duplication and self-dual parity prediction are considered in detail. As a method for the reduction of self-dual outputs, output space compaction of self-dual outputs is considered. For the first time we also describe in this paper how a self-dual circuit can be modified into a self-dual fault-secure circuit.

Experimental Results for Self-Dual Multi-Output Combinational Circuits

In this short note, the possibilities and the limitations for the application of self-dual circuits with alternating inputs are experimentally investigated. The original circuit is assumed to be given as a netlist of gates. The necessary area overhead, the fault coverage for single stuck-at faults in test mode and the error detection probability in on-line mode due to internal stuck-at faults and stuck-at faults at the input lines are determined for MCNC benchmark circuits.