Michael Goessel

Low cost concurrent error detection for the advanced encryption standard

We present a new low-cost concurrent checking method for the advanced encryption standard (AES) encryption algorithm. In this method, the parity of the 128-bit input is determined and modified step-by-step into the parity of the 128-bit output according to the processing steps of the AES encryption. For the parity-preserving AES steps shift-rows and mix-column no parity modifications are necessary. The modified parity is compared in any round with the actual parity of the outputs of the round. To obtain the hardware costs we implemented this method on a Xilinx Virtex 1000 FPGA. For this implementation, the hardware overhead is about 8% and the additional time delay is about 5%. The method detects technical faults and deliberately injected faults during normal operation.

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption algorithms. In this paper we will describe parity code based concurrent error detection (CED) approach against such attacks in substitution-permutation network (SPN) symmetric block ciphers [22]. The basic idea compares a carefully modified parity of the input plain text with that of the output cipher text resulting in a simple CED circuitry. An analysis of the SPN symmetric block ciphers reveals that on one hand, permutation of the round outputs does not alter the parity from its input to its output. On the other hand, exclusive-or with the round key and the non-linear substitution function (s-box) modify the parity from their inputs to their outputs. In order to change the parity of the inputs into the parity of outputs of an SPN encryption, we exclusive-or the parity of the SPN round function output with the parity of the round key. We also add to all s-boxes an additional 1-bit binary function that implements the combined parity of the inputs and outputs to the s-box for all its (input, output) pairs. These two modifications are used only by the CED circuitry and do not impact the SPN encryption or decryption. The proposed CED approach is demonstrated on a 16-input, 16-output SPN symmetric block cipher from [1].

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.

Self-Checking Combinational Circuits with Unidirectionally Independent Outputs

In this paper we propose a structure dependent method for the systematic design of a self-checking circuit which is well adapted to the fault model of single gate faults and which can be used in test mode.

Self-dual parity checking-A new method for on-line testing

Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a self-dual complement of a given Boolean function. The parity prediction function f/sub p/ of ordinary parity checking is replaced by the self-dual complement /spl delta//sub p/ of this function such that the module-2 sum of the outputs of the monitored circuit and of /spl delta//sub p/ is an arbitrary self-dual Boolean function h. Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement /spl delta//sub p/ is small. Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs. The fault coverage of this method is almost the same as for parity checking. The usefulness of the proposed method is demonstrated for MCNC benchmark circuits.

An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment

We present a new scan-BIST approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test. Two MISRs (multiple-input signature registers) are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and non-failing intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We present analytical results to determine an appropriate interval length and the degree of overlap, an upper bound on the size of S, and a lower bound on the number of true failing vectors; the latter depends only on the knowledge of failing and non-failing intervals. Finally, we describe two pruning procedures that allow us to reduce the size of S, while retaining most true failing vectors in S. We present experimental results for the ISCAS 89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.

Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques

This paper introduces the concept of utilizing the timing flexibility of automatic test equipment (ATE) when designing X-tolerant test compactors. Redundant information is generated by the compactor and transferred to the ATE at a frequency k times higher than the scan shift frequency. This technique is different than current X-tolerant compactors where the necessary redundant information is generated on additional compactor outputs. If the Compactor design can take into account the ATE capabilities, the knowledge of the redundancy can be efficiently used. The ATE will select the relevant information out of the compacted test response, which then leads to a reduction of the ATE compare data by a factor k. In the best case this method can be applied without extra costs related to the higher frequency. The benefit of this approach is a higher parallel test factor due to the reduced number of output pins. This paper explains the capabilities of the employed ATE which need to be taken into account when designing an X-tolerant compactor using a higher output data rate. The method is also demonstrated on a shift register which works at a multiple of the scan shift frequency.

On-chip evaluation, compensation and storage of scan diagnosis data

Technology and product ramp-up suffers increasingly from systematic production defects. Diagnosis of scan-test fail data plays an important role in yield enhancement, as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production may lead to significant test time overhead. A new on-chip architecture is presented that evaluates scan-test results and stores relevant scan diagnostic information on chip. Scan diagnostic data is unloaded for offline analysis after the scan test has been finished. Unloading scan diagnostic data from chip requires only very little test time overhead. Moreover, the proposed technique is automatic test equipment independent and accelerates test program development. A detailed implementation example, based on a state-of-the-art SoC device, is given.

Test Set Enrichment using a Probabilistic Fault Model and the Theory of Output Deviations

We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theory of output deviations, can be used to supplement tests for classical fault models, thereby increasing test quality and reducing the probability of test escape. Output deviations can also be used for test selection, whereby the most effective test patterns can be selected from large test sets during time-constrained and high-volume production testing. Experimental results are presented to evaluate the effectiveness of patterns with high output deviations for the single stuck-at and bridging fault models

Masking of X-Values by Use of a Hierarchically Configurable Register

In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1. This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.