Vadim Geurkov

Multi-parametric optimisation of the modular computer architecture

The paper describes an approach that allows optimisation of computing architecture selection in case of multi-parametric requirements. The proposed method is oriented to systems combined from modular components. The approach is based on decomposition of a multi-dimensional design space into multiple two-dimensional subdesign spaces. The paper presents the procedure that drastically reduces the number of architectural variants to be analysed. This has become possible by the presentation of each subdesign space in a form of a tree, hierarchical arrangement, and further pruning of subdesign spaces. The proposed approach is applicable to any system architecture based on modules with known performance parameters. As a result, the proposed method has allowed selection of the architecture, which satisfies multiple performance constrains (e.g., performance, cost, power consumption, reliability, etc.), in a small time range. The implementation of the method for the architectural optimisation of the reconfigurable data-stream processors, which are based on the Field Programmable Gate Array (FPGA) devices, is also discussed.

Dynamic behavior of resistive faults in nanometer technology

Modeling the dynamic behavior for resistive shorts and opens at switch-level dictates the characterization of enhanced delay due to these faults with respect to the input combinations, fault sites, defect resistance and technology variation. The resistive fault model is applied to CMOS technologies with feature sizes of 350 nm, 180 nm, 90 nm, 45 nm and 32 nm, respectively. This model is targeted to transistor-level CMOS circuits. A static defect in a circuit (shorts or opens) is replaced by a resistor and a simple electrical analysis of the circuit is performed to obtain the timing variations which occurred during propagation of a logic value from gate inputs to gate output.

Reed-Solomon encoder & decoder design, simulation and synthesis

Truth of information in any communication system is very critical. Use of forward error correction (FEC) to lower the probability of error and increase transmission distance has become common. Reed-Solomon is a block FEC, capable of correcting multiple errors, specifically focusing on burst errors, making it widespread for storage devices, and wireless and mobile communication units. This paper presents an implementation of a (7,3) Reed-Solomon encoder-decoder using VHSIC hardware description language (HDL). The encoder downloaded into Altera MAX 7128 CPLD for functional and timing verification, and decoder is ready for fabrication.

A multi-mode video-stream processor with cyclically reconfigurable architecture

This paper presents an approach for development of cost-effective hardware platform for video/image processing. The approach utilizes the SRAM based reconfigurable logic devices (FPGAs) and, their capability of run-time temporal partitioning of logic resources. We propose the architecture for multi-mode video-stream processor with cyclically reconfigurable structure. The proposed architecture has been analyzed on the basis of experiments conducted on AMIRIX AP1000 development system based on Xilinx Virtex-2Pro FPGA. Multi-mode Adaptive Reconfigurable System has been developed, based on Xilinx Virtex-4 FPGA. This platform is capable of supporting the runtime temporal partitioning of on-chip resources. The main component of the research was the introduction of methodology of design for cyclically reconfigurable processor that uses the temporal partitioning mechanism (TPM). TPM allows reuse of the logic and routing resources of an SRAM based FPGA device by the means of partitioning algorithm in to tasks and execution of these tasks in different time slots. This technique allows the reduction of size requirement for FPGA devices, as well as, increase in cost efficiency, and decrease in power consumption of the system compared to systems with statically configured FPGA devices. Applications associated with stereo-vision algorithms and object tracking have been developed and tested on the platform. Finally, the analysis of the cost-effectiveness of this approach has been conducted. This analysis has demonstrated sufficient increase of efficiency in comparison to statically configured FPGA designs. Work also presents optimal conditions at which the use of the architecture would be most cost effective, and where the use of it would be most beneficial. The experimental tests have been done by the means of development of application that are used in the industry in the area of stereo-vision space-born applications.

Multilevel Radiation Protection of Partially Reconfigurable Field Programmable Gate Array Devices

Protection of on-board computing platforms from radiation effects is a complex problem. However, the cost of hardware failure in high-performance computers usually is very high, because it can result in billons of operations being lost within one second of system stall or even in mission failure. Traditional approaches based on redundant hardware and mechanical shielding can be very costly and still cannot guarantee full protection of high-performance computing platforms from radiation. Instead, we propose an approach based on run-time self-restoration of digital computing circuits allocated in partially reconfigurable field programmable gate array devices (FPGA). A novel approach is presented that allows sustaining the performance of the run-time reconfigurable stream processing system at its maximum level. This becomes possible by development of a multilevel self-restoration mechanism based on self-assembling/reassembling the virtual hardware components inside the FPGA in run time. This approach allows restoration from transient and permanent hardware faults without or with optimum performance degradation. However, at this stage of the project the fault detection aspect was not considered. All levels of the proposed mechanism were investigated and tested on the prototype reconfigurable computing platform. This platform was developed on a base of XILINX Virtex FPGA devices. Analysis of results shows that the developed mechanism of self-restoration allows very fast (run-time) restoration of functionality. On the other hand, it dramatically increases the lifetime of FPGA based space-borne computing platforms.

Design of a 4-bit programmable delay with TDC-based BIST for use in serial data links

Time mode signal processing (TMSP) in general is defined as the manipulation of sampled analog signal information using time difference variable. TMSP allows one to implement analog signal processing functions using the most basic element available, namely, propagation delay. A time to digital converter (TDC) is used to convert the time difference between two edges of two signals into a sequence of digital numbers. TDCs have been extensively used in designing laser range finders, all digital phase locked loops (ADPLL), frequency synthesizers, analog to digital converters (ADC), SerDes, etc. This paper proposes a new approach that utilizes a TDC for detection of potential stuck-at faults in a 4-bit programmable delay to be used in designing a time mode SerDes. Moreover, the proposed approach suggests that, when any circuit needs to delay a certain signal, it can be confirmed whether the amount of delay is correctly enforced by utilizing a TDC module and translating the difference between the main signal and the delayed version of the signal into a sequence of bits. Then, one can observe if the generated bits correspond to a correct operation of the circuitry in charge of delaying the main signal.

Optimal choice of arithmetic compactors for mixed-signal systems

Compaction circuits that have been used for mixed-signal systems testing constitute a part of encoding/decoding device for an arithmetic error-control code (ECC). These circuits are commonly referred to as residue computing circuits (RCCs). As ECCs originated primarily to protect data transfers over binary channels, their design methodology has been mostly oriented towards a binary case. A non-binary design technique has only been considered for a special type of compaction modulus. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. It is assumed that the data being compacted are fuzzy. This in turn distorts the result of compaction increasing the aliasing rate. Even though the fault free systems distortion is small, the compaction circuit may aggravate it beyond the acceptable levels making the method impractical. We design a low cost compactor that does not increase the distortion. The circuit can be used for off-line and on-line mixed-signal testing, as well as fault-tolerant data processing and noise-tolerant data transmission.

Cost effective reconfigurable architecture for stream processing applications

This paper presents an approach for development of cost-effective custom video/image processing systems. The approach utilizes the concept of temporal partitioning of resources in the partially reconfigurable FPGA devices. Paper proposes architecture of the multi-mode video-stream processor with cyclically reconfigurable structure. The cost-effectiveness of the proposed approach has been analyzed on the basis of experiments conducted on multi-mode adaptive reconfigurable system (MARS) platform that was developed for that purpose. The video-processing cores associated with stereo-vision algorithms have been developed, tested and analyzed. The experiments have shown that the cost-effectiveness of the systems based on proposed approach can be better than the traditional approaches based on large statically configured FPGAs.

Arithmetic compaction circuits for mixed-signal systems testing

Arithmetic error-control codes (ECCs) have been designed to protect the integrity of data being transmitted and/or processed. The implementation of an ECC involves constructing an appropriate encoding/decoding device. An important part of this device is a residue computing circuit (RCC). This circuit has also been used in mixed-signal systems testing and is referred to as a compaction circuit. As ECCs originated primarily to protect data transfers over binary channels, the design methodology for RCCs has been mostly oriented toward a binary case. A non-binary design technique has only been reported for a special type of compaction modulus. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. It is assumed that the codes being compacted are fuzzy, which distorts the result of compaction and increases the aliasing rate. Even though the fault free systems output code distortion is small, the compaction circuit may aggravate it beyond the acceptable levels making the method impractical. We design a low cost compactor that does not increase the code distortion. The circuit can be used for off-line and on-line mixed-signal systems testing, as well as fault-tolerant data processing and noise-tolerant data transmission.

Built-in-test for integrating analog-to-digital converters that utilize a phase-sensitive detector

Integrating analog-to-digital converters that utilize a phase-sensitive detector (PSADCs) are frequently used in high precision instrumentation and measurement systems. As any technical object, a PSADC is subject to faults. These faults must be detected promptly and accurately by built-in low complexity hardware. In the present work, this objective is achieved by the adoption of error-control codes. Off-line and on-line test methods are explored. We demonstrate how to perform compaction in digital and analog domains. We design a compactor of analog signals on the basis of a PSADC and explain how to utilize coding redundancy for on-line testing. We also explain how to use a PSADC for generating multiple residues which can further be processed by a computing device operating in a residue number system (RNS). Compared to existing techniques, the proposed approach is characterized by higher accuracy and lower latency. The proposed device can be used for analog circuits testing in much the same way as a conventional signature analyzer is used for digital circuits testing. The test process involves measuring signatures of analog signals, which ultimately appear in digital form. The signatures are then verified to make a pass/fail decision.