Lev Kirischian

Multi-parametric optimisation of the modular computer architecture

The paper describes an approach that allows optimisation of computing architecture selection in case of multi-parametric requirements. The proposed method is oriented to systems combined from modular components. The approach is based on decomposition of a multi-dimensional design space into multiple two-dimensional subdesign spaces. The paper presents the procedure that drastically reduces the number of architectural variants to be analysed. This has become possible by the presentation of each subdesign space in a form of a tree, hierarchical arrangement, and further pruning of subdesign spaces. The proposed approach is applicable to any system architecture based on modules with known performance parameters. As a result, the proposed method has allowed selection of the architecture, which satisfies multiple performance constrains (e.g., performance, cost, power consumption, reliability, etc.), in a small time range. The implementation of the method for the architectural optimisation of the reconfigurable data-stream processors, which are based on the Field Programmable Gate Array (FPGA) devices, is also discussed.

Run-Time Recovery Mechanism for Transient and Permanent Hardware Faults Based on Distributed, Self-Organized Dynamic Partially Reconfigurable Systems

Field-Programmable Gate Arrays (FPGAs) are rapidly gaining popularity as implementation platforms for complex space-borne computing systems. However, such systems are exposed to cosmic radiation with levels orders of magnitude higher than terrestrial levels which can cause transient and even permanent hardware faults in on-board computing platforms. Because of this, development of effective fault mitigation methods and self-repair mechanisms has become a vital aspect for FPGA-based space-borne computing platforms. This work presents a novel method for transient and permanent fault mitigation and run-time fault recovery for commercial-grade FPGA devices with partially reconfigurable tile-based architectures. The proposed method ensures the same pre-determined recovery time for transient and permanent hardware faults through dynamic on-chip component relocation regardless of the fault type. The method makes use of fully distributed control, communication, self-synchronization and self-integration mechanisms embedded in each on-chip hardware component. Run-time collaboration between components provides relocation & fault mitigation procedures. The distributed nature of the above mechanisms excludes most central failure points which could cause non-restorable system faults. This method has been implemented, tested and verified on a Xilinx Kintex-7 FPGA platform. Results show that the proposed method is significantly more resource efficient when compared with Triple-Module Redundancy or central, software-based control mechanisms.

A framework of embedded reconfigurable systems based on re-locatable virtual components

The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance.

SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units

For most multi-modal stream processing tasks Dynamic Reconfigurable Systems-on-Chip (SoC) have demonstrated high efficiency in cost and power. These systems utilize partial reconfiguration for dynamic adaptation to changes in the workload or in environment. Mostly, reconfiguration mechanisms are based on central resource management sub-systems deployed in a CPU-core. In this paper we propose a novel mechanism for SoC self-integration based on Collaborative Macro-Function Units (CMFU). Each CMFU consist of a function-specific IP-core combined with a Co-op unit. Co-op units allow CMFUs to co-operate with each other and provide run-time self-integration into the SoC. As well, they provide self-initiation, self-termination and self-synchronization procedures without any central control. This allows a dramatic increase in SoC flexibility, reliability and, finally, survivability. It is specifically important to mitigate hardware faults caused by radiation effects or aging of the die. The proposed mechanism was implemented and tested on a Xilinx Kintex-7 FPGA platform. It was shown that CMFUs can perform self-integration and relocation inside the FPGA almost seamlessly. The hardware overhead of the Co-op unit was relatively small (less than 10% of the entire CMFUs).

Decentralized run-time recovery mechanism for transient and permanent hardware faults for space-borne FPGA-based computing systems

One of the most important problems for mission critical space-borne computing systems employing FPGA devices is fault tolerance to transient and permanent hardware faults. In many cases, the ability for run-time self-recovery from such faults is a vital feature. This paper presents a method and mechanism for run-time recovery of FPGA-based System-on-Chip (SoC) based on Collaborative Macro-Function Units (CMFUs). Each CMFU consist of a macro-function specific data-path, control unit and circuits providing self-integration, self-synchronization and self-recovery functions for the CMFU, without centralized control. The proposed mechanism allows run-time scrubbing or relocation of faulty components of the SoC providing much higher flexibility and reliability of the system. This mechanism was implemented and tested on a Xilinx Kintex-7 FPGA platform. It was determined that the proposed approach can provide seamless run-time recovery for pipelined SoCs, while being transparent to the application.

A multi-mode video-stream processor with cyclically reconfigurable architecture

This paper presents an approach for development of cost-effective hardware platform for video/image processing. The approach utilizes the SRAM based reconfigurable logic devices (FPGAs) and, their capability of run-time temporal partitioning of logic resources. We propose the architecture for multi-mode video-stream processor with cyclically reconfigurable structure. The proposed architecture has been analyzed on the basis of experiments conducted on AMIRIX AP1000 development system based on Xilinx Virtex-2Pro FPGA. Multi-mode Adaptive Reconfigurable System has been developed, based on Xilinx Virtex-4 FPGA. This platform is capable of supporting the runtime temporal partitioning of on-chip resources. The main component of the research was the introduction of methodology of design for cyclically reconfigurable processor that uses the temporal partitioning mechanism (TPM). TPM allows reuse of the logic and routing resources of an SRAM based FPGA device by the means of partitioning algorithm in to tasks and execution of these tasks in different time slots. This technique allows the reduction of size requirement for FPGA devices, as well as, increase in cost efficiency, and decrease in power consumption of the system compared to systems with statically configured FPGA devices. Applications associated with stereo-vision algorithms and object tracking have been developed and tested on the platform. Finally, the analysis of the cost-effectiveness of this approach has been conducted. This analysis has demonstrated sufficient increase of efficiency in comparison to statically configured FPGA designs. Work also presents optimal conditions at which the use of the architecture would be most cost effective, and where the use of it would be most beneficial. The experimental tests have been done by the means of development of application that are used in the industry in the area of stereo-vision space-born applications.

Multilevel Radiation Protection of Partially Reconfigurable Field Programmable Gate Array Devices

Protection of on-board computing platforms from radiation effects is a complex problem. However, the cost of hardware failure in high-performance computers usually is very high, because it can result in billons of operations being lost within one second of system stall or even in mission failure. Traditional approaches based on redundant hardware and mechanical shielding can be very costly and still cannot guarantee full protection of high-performance computing platforms from radiation. Instead, we propose an approach based on run-time self-restoration of digital computing circuits allocated in partially reconfigurable field programmable gate array devices (FPGA). A novel approach is presented that allows sustaining the performance of the run-time reconfigurable stream processing system at its maximum level. This becomes possible by development of a multilevel self-restoration mechanism based on self-assembling/reassembling the virtual hardware components inside the FPGA in run time. This approach allows restoration from transient and permanent hardware faults without or with optimum performance degradation. However, at this stage of the project the fault detection aspect was not considered. All levels of the proposed mechanism were investigated and tested on the prototype reconfigurable computing platform. This platform was developed on a base of XILINX Virtex FPGA devices. Analysis of results shows that the developed mechanism of self-restoration allows very fast (run-time) restoration of functionality. On the other hand, it dramatically increases the lifetime of FPGA based space-borne computing platforms.

SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations

Field-programmable gate arrays are becoming one of the implementation platforms of choice for computationally intensive embedded applications, such as multimode stream processors; such systems often exhibit poor cost-efficiency as various system modules can be idle, based on operating mode. This problem can be addressed through the use of reconfigurable computing, which allows underlying logic resources to be shared among system modules; using this approach, an application and mode specific processor can be generated at run-time. However, this generation process can interfere with application workloads; this is particularly true in the case of high data-rate stream processors. To address this problem, this brief presents a system-on-programmable-chip self-integration mechanism aimed at reconfigurable stream processors. The proposed mechanism is implemented using a distributed architecture and the multimode adaptive collaborative reconfigurable self-organized system framework. The mechanism arranges configuration, link establishment, and scheduling tasks around the stream workload, which allows for seamless run-time architecture adaptation. When compared with traditional approaches, based on central, instruction-based sequential processors, the proposed approach is shown to offer a faster (up to 10 times) link establishment and the scheduling capabilities; more importantly, the proposed mechanism can offer seamless run-time architecture adaptation by allowing the overlap of processing and configuration tasks.

Lowering power consumption using run-time reconfiguration for stereo rectification

Trends of high power usage in portable consumer electronics and high speed designs is an important factor that biases the selection of an ASIC over a FPGA. ASICs are optimized to minimize the amount of logics used for a particular application; reductions in power are noticed when compared against FPGAs design for the same application. On the other hand, some FPGAs equipped with run-time reconfiguration, allow portions of the design to be changed on the fly. Having an appropriate methodology which creates a micro-level static architecture and reduces the reconfiguration overhead is used to lower the power consumption. This can allow the FPGA designs to be somewhat competitive against ASIC designs. This paper explores the reconfiguration methodology to lower the power consumption for the application of stereo rectification. The results obtained show significant savings in logical resources and power consumption when compared to ASIC-like FPGA implementations.

Mitigation of variations in environmental conditions by SoPC architecture adaptation

Run-time reconfigurable computing systems can offer increased flexibility when compared with traditional systems, a feature which can make them attractive for space-borne computing applications. This flexibility can allow a system to adapt to changes in operating conditions, such as reductions in available power, reductions in available resources (wither due to increases in task deployment, or due to permanent faults) or changes in required performance (processing rate). A unified mechanism which allows such adaptations is presented in this paper, based on the concept of architectural variants for a given algorithm; the different architectures exhibit different resource utilization, performance and power consumption attributes. This allows the system to meet various constraints through the judicious selection and deployment of an architecture variant by the appropriate reconfiguration of an implemented System-on Programmable Chip (SoPC). The adaptive capabilities of the proposed mechanism are experimentally tested on the Xilinx Kintex-7 FPGA platform (KC-705) using a video processing application aimed at 720p video streams. Three different versions of the application algorithm are implemented, allowing for performance variations between 3 and 300+ frames/second, while exhibiting a large power consumption range (from 1 mW to 81 mW).