Valeri Kirischian

Multi-parametric optimisation of the modular computer architecture

The paper describes an approach that allows optimisation of computing architecture selection in case of multi-parametric requirements. The proposed method is oriented to systems combined from modular components. The approach is based on decomposition of a multi-dimensional design space into multiple two-dimensional subdesign spaces. The paper presents the procedure that drastically reduces the number of architectural variants to be analysed. This has become possible by the presentation of each subdesign space in a form of a tree, hierarchical arrangement, and further pruning of subdesign spaces. The proposed approach is applicable to any system architecture based on modules with known performance parameters. As a result, the proposed method has allowed selection of the architecture, which satisfies multiple performance constrains (e.g., performance, cost, power consumption, reliability, etc.), in a small time range. The implementation of the method for the architectural optimisation of the reconfigurable data-stream processors, which are based on the Field Programmable Gate Array (FPGA) devices, is also discussed.

A multi-mode video-stream processor with cyclically reconfigurable architecture

This paper presents an approach for development of cost-effective hardware platform for video/image processing. The approach utilizes the SRAM based reconfigurable logic devices (FPGAs) and, their capability of run-time temporal partitioning of logic resources. We propose the architecture for multi-mode video-stream processor with cyclically reconfigurable structure. The proposed architecture has been analyzed on the basis of experiments conducted on AMIRIX AP1000 development system based on Xilinx Virtex-2Pro FPGA. Multi-mode Adaptive Reconfigurable System has been developed, based on Xilinx Virtex-4 FPGA. This platform is capable of supporting the runtime temporal partitioning of on-chip resources. The main component of the research was the introduction of methodology of design for cyclically reconfigurable processor that uses the temporal partitioning mechanism (TPM). TPM allows reuse of the logic and routing resources of an SRAM based FPGA device by the means of partitioning algorithm in to tasks and execution of these tasks in different time slots. This technique allows the reduction of size requirement for FPGA devices, as well as, increase in cost efficiency, and decrease in power consumption of the system compared to systems with statically configured FPGA devices. Applications associated with stereo-vision algorithms and object tracking have been developed and tested on the platform. Finally, the analysis of the cost-effectiveness of this approach has been conducted. This analysis has demonstrated sufficient increase of efficiency in comparison to statically configured FPGA designs. Work also presents optimal conditions at which the use of the architecture would be most cost effective, and where the use of it would be most beneficial. The experimental tests have been done by the means of development of application that are used in the industry in the area of stereo-vision space-born applications.

Multilevel Radiation Protection of Partially Reconfigurable Field Programmable Gate Array Devices

Protection of on-board computing platforms from radiation effects is a complex problem. However, the cost of hardware failure in high-performance computers usually is very high, because it can result in billons of operations being lost within one second of system stall or even in mission failure. Traditional approaches based on redundant hardware and mechanical shielding can be very costly and still cannot guarantee full protection of high-performance computing platforms from radiation. Instead, we propose an approach based on run-time self-restoration of digital computing circuits allocated in partially reconfigurable field programmable gate array devices (FPGA). A novel approach is presented that allows sustaining the performance of the run-time reconfigurable stream processing system at its maximum level. This becomes possible by development of a multilevel self-restoration mechanism based on self-assembling/reassembling the virtual hardware components inside the FPGA in run time. This approach allows restoration from transient and permanent hardware faults without or with optimum performance degradation. However, at this stage of the project the fault detection aspect was not considered. All levels of the proposed mechanism were investigated and tested on the prototype reconfigurable computing platform. This platform was developed on a base of XILINX Virtex FPGA devices. Analysis of results shows that the developed mechanism of self-restoration allows very fast (run-time) restoration of functionality. On the other hand, it dramatically increases the lifetime of FPGA based space-borne computing platforms.

Cost effective reconfigurable architecture for stream processing applications

This paper presents an approach for development of cost-effective custom video/image processing systems. The approach utilizes the concept of temporal partitioning of resources in the partially reconfigurable FPGA devices. Paper proposes architecture of the multi-mode video-stream processor with cyclically reconfigurable structure. The cost-effectiveness of the proposed approach has been analyzed on the basis of experiments conducted on multi-mode adaptive reconfigurable system (MARS) platform that was developed for that purpose. The video-processing cores associated with stereo-vision algorithms have been developed, tested and analyzed. The experiments have shown that the cost-effectiveness of the systems based on proposed approach can be better than the traditional approaches based on large statically configured FPGAs.

Two Photon Absorption Laser Facility for Single Event Effect Testing

The laser facility for single event effect (SEE) testing at the Saskatchewan Structural Sciences Centre is introduced. Its capabilities of studying SEEs via two photon absorption (TPA) are described. Data on a Virtex-5 FPGA are provided.

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream.

Single event upset characterization of the Tegra K1 mobile processor using proton irradiation

Vroton induced SEU cross-sections of Tegra K1 mobile processor are presented. Overall upset rates of Tegra K1 in the space radiation environment are estimated.

High energy proton irradiation results for the DSP cores of the KeyStone II system-on-chip (SoC) 66AK2L06

Vroton induced SEU cross-section of DSP cores within the KeyStone™ II system-on-chip 66AK2L06 is presented. Upset rates in the space radiation environment are estimated.

Single event upset characterization of the Zynq UltraScale+ MPSoC using proton irradiation

Proton induced SEU cross-sections of the SRAM which stores the logic configuration and certain functional blocks of the Zynq UltraScale+ MPSOC are presented. Upset rates in the space radiation environment are estimated.

Laser Single Event Effects Response of Optek and Infineon Hall Effect Sensors

Single photon absorption laser single event effects test results for the Optek and Infineon Hall Effect Sensors are presented. The results are compared to previously published heavy ion data for the Optek sensor.