Vagner S. Rosa

FPGA Design of A H.264/AVC Main Profile Decoder for HDTV

This paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all folly H.264/AVC compliant, were completely described in VHDL and forther validated through simulations down to prototyping. The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications

VHDL generation of optimized FIR filters

This work proposes an VHDL generation software for optimized FIR filters. In this paper a near optimum algorithm for constant coefficient FIR filters was used. This algorithm uses general coefficient representation for the optimal sharing of partial products in Multiple Constants Multiplications (MCM). The developed tool was compared to Matlab FDA toolbox. Synthesis results show that our tool is able to produce significantly better hardware than FDA toolbox, doubling the speed and reducing the silicon area by 75%. The software produces a generic VHDL output, synthesizable to ASIC or FPGA.

Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.

A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis

This paper presents the design and implementation of a dedicated hardware architecture for binary arithmetic decoder (BAD) engines of CABAD, as defined in the H.264/AVC video compression standard. The BAD is the most important CABAD process, which is the main entropy encoding method defined by the H.264/AVC standard. The BAD is composed by tree engines: Regular, Bypass and Terminate. A large set of software experiments was made to profile each engine. Based on bitstream flow analysis a new dedicated hardware architecture was proposed to improve the hardware efficiency of BAD engines. The proposed solution was described in VHDL and synthesized to a Xilinx Virtex2-Pro FPGA. The results show that the developed architecture reaches 103 MHz, and delivers up to 4 bins per cycle in bypass engines, against 2 bins per cycle as exposed in the literature.

A low-cost hardware architecture binarizer design for the H.264/AVC CABAC entropy coding

This paper presents two hardware architectures design for the binarizer part of the CABAC (Context-Based Adaptive Binary Arithmetic Coding) entropy encoder as defined in the H.264/AVC video compression standard. The architectures proposed in this paper are able to reach the Level 4.2 processing requirements of the standard specification, achieving processing rates of 103,9 Mbins/s. The proposed solutions can save on average 50% hardware resources, mainly because a new technique to enable the reuse of hardware is applied, avoiding the support of the Kth order Exp-Golomb encoder.

Performance evaluation of parallel FIR filter optimizations in ASICs and FPGA

This paper addresses constant coefficients parallel FIR filter optimizations. The optimizations proposed use a combination of two approaches: the reduction of the coefficients to a limited number of power-of-two (PT) terms, where the maximum number of non-zero bits is set as a constraint, followed by common sub-expression elimination (CSE) among multipliers. Implementation results and the optimization effects in area, delay, and power for FPGAs and CMOS standard cells designs are presented. We show that it is possible to achieve area savings for both, ASIC or FPGAs implementation. Additional results for ASIC area are compared when timing constrained physical synthesis from a 0.35mum CMOS cell library is performed

FPGA Prototyping Strategy for a H.264/AVC Video Decoder

This paper presents the prototyping strategy used to validate the designed modules of a main profile H.264/AVC video decoder designed to achieve 1080p HDTV resolution, implemented in a FPGA. All modules designed were completely described in VHDL and further validated through simulations. The post place-and-route synthesis results indicate that the designed architectures are able to target real time when processing HDTV 1080p frames (1080times1920). The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The prototyping strategy used an embedded Power PC and associated logic and buffering to control the modules under prototyping. A host computer, running the reference software, was used to generate the input stimuli and to compare the results, through a RS-232 serial interface.

A High Performance Parallel FIR Filters Generation Tool

This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation targeted for high performance. The generation tool employ a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, where the maximum number of non-zero in each coefficient is taken as a constraint, followed by common subexpression elimination (CSE) among multipliers. Synthesis results for a range of different filter specifications, using Quartus II FPGA synthesis tool are presented

Welding Groove Mapping - Implementation and Evaluation of Image Processing Algorithms on Shiny Surfaces

Electric arc welding is a key process in the heavy steel industries. It is a very complex task that demands a high degree of control in order to meet the international standards for fusion welding. We propose a Vision-Based Measurement (VBM) system and evaluate how different algorithms impact the results. The proposed system joins hardware and software to image the welding plates using a single CMOS camera, run computer vision algorithms and control the welding equipment. A complete prototype, using a commercial linear welding robot is presented. The evaluation of the system as a groove mapping equipment, considering different processing algorithms combined with noise removal and line segment detection techniques, allows us to define the appropriated approach for shop floor operation, combining low asymptotic cost and measurement quality.

An HDTV H.264 deblocking filter in FPGA with RGB video output

This paper presents an architecture for implementing the H.264 Deblocking Filter with RGB output in FPGA, exceeding HDTV requirements when synthesized to a target FPGA. The goal of the design was to achieve the HDTV requirements, designing a deep pipelined architecture that makes a balanced use of the resources available in the target FPGA architecture. When synthesized to VirtexII-pro FPGA, the developed architecture used only 1800 logic cells and achieved 71 frames per second at 1080p HDTV resolution (1920x1080).