Valeria Garofalo

Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error

Truncated multipliers compute the n most-significant bits of the n × n bits product. This paper focuses on variable-correction truncated multipliers, where some partial-products are discarded, to reduce complexity, and a suitable compensation function is added to partly compensate the introduced error. The optimal compensation function, that minimizes the mean square error, is obtained in this paper in closed-form for the first time. A sub optimal compensation function, best suited for hardware implementation, is introduced. Efficient multipliers implementation based on sub-optimal function is discussed. Proposed truncated multipliers are extensively compared with previously proposed circuits. Experimental results, for a 0.18 μm technology, are also presented.

Design of Fixed-Width Multipliers With Linear Compensation Function

This paper focuses on fixed-width multipliers with linear compensation function by investigating in detail the effect of coefficients quantization. New fixed-width multiplier topologies, with different accuracy versus hardware complexity trade-off, are obtained by varying the quantization scheme. Two topologies are in particular selected as the most effective ones. The first one is based on a uniform coefficient quantization, while the second topology uses a nonuniform quantization scheme. The novel fixed-width multiplier topologies exhibit better accuracy with respect to previous solutions, close to the theoretical lower bound.

Low error truncated multipliers for DSP applications

The paper presents a new technique to design signed and unsigned truncated multipliers. Simple formulae are developed in the paper to describe the truncated multiplier with minimum mean square error for every inputspsila bit-width. With respect to previously proposed techniques, our analytical approach is more general and improves the accuracy of the multiplier. We have also compared the accuracy achievable with the proposed truncated multiplier with respect to the accuracy of a standard full-width multiplier in a typical DSP application. The results show that the proposed multiplier causes only a negligible loss in accuracy. On the other hand, the area and the power dissipation of the DSP datapath are both improved by 16%.

A novel truncated squarer with linear compensation function

A truncated binary squarer is a squarer with a n bit input that produces a n bit output. The proposed design minimizes the mean square error of the squarer and results in a very simple and fast circuital implementation. The squarer, compared against state of the art circuits, provides a reduction of the mean square error ranging from 20% to 5%. At the same time, the proposed squarer is able to reduce the power dissipation, reduce the silicon area occupation, and increase the maximum working frequency. Implementations results are provided for a 0.18µm technology.

Fixed-width multipliers for the implementation of efficient digital FIR filters

The use of fixed-width multiplier for the implementation of FIR filters is investigated in this paper. The paper presents a review of the existing fixed-width multiplier architectures and analytically calculates the error introduced by the use of fixed-width multipliers in the realization of FIR filters. FIR filters are implemented in TSMC 0.18@mm technology using state-of-the-art fixed-width multipliers, varying the architecture and the width of the output. The analysis shows that fixed-width multipliers are a suitable replacement for the full-width multiplier. Furthermore the best trade-off between error, silicon area occupation and power is provided by the LMS fixed-width multiplier. As example a FIR filter with 16b fixed-width multiplier provides a reduction of 16% in area and 18% in power dissipation with a 22% increase of the working frequency, while keeping the mean square error below 14LSB^2.

Fixed-width CSD multipliers with minimum mean square error

Many multimedia and DSP applications require fixed-width multipliers, in which input data and output results have the same bit width. In this paper we investigate fixed-width multipliers where one of the input operand is a constant, encoded using canonic signed digit (CSD) representation. This is a very important case in many practical applications such as the calculation of Fast Fourier Transform. In the paper we derive in closed form the expression of the compensation function giving the minimum mean square error for CSD fixed-width multiplier. On the basis of this analytical result, we propose a hardware efficient implementation of the multiplier. Fixed width CSD multipliers implemented with the approach presented in this paper are accurate and can be implemented by using a simple partial-product reduction tree followed by a fast adder, without requiring additional look-up tables. The proposed approach is general and is well suited for implementation in circuit synthesizers. Implementation results in 90nm technology are presented, to demonstrate the effectiveness of the proposed technique.

High-speed differential resistor ladder for A/D converters

This paper describes the implementation of a novel high-speed differential resistor ladder suited for A/D converters. The novel ladder yields, theoretically, up to a sixteen-fold reduction of the propagation delay with respect to the conventional differential ladder. Simulation results, for a BiCMOS 0.25μm technology, show that the novel ladder results in a fivefold increase of the maximum sampling frequency when employed to design a 8-bit Flash converter. A 70% higher speed is also highlighted when the ladder is employed in a Folding and Interpolating 8-bit converter.

Code compression for ARM7 embedded systems

A detailed analysis of different code compression algorithms is provided in this paper. The performances of the algorithms have been tested on ARM codes whose size is below 32 KB. Code compression performances have been considered including the compression overheads due to the decoding tables, to the alignment and to the tables for random access to the compressed code. We have analyzed Huffman, Tunstall, LZ77 and Class-based techniques. Optimal performances are provided by Class Based algorithms with an average compression ratio of 64%. For this algorithm we have realized a static decompression engine that provides, after an initial latency of three clock cycles, one 32b instruction for clock cycle.

Constrained piecewise polinomial approximation for hardware implementation of elementary functions

This paper presents a novel technique for designing piecewise polynomial interpolators for hardware implementation of elementary functions. In the proposed approach, we impose special constraints between polynomial coefficients of adjacent segments. This allows to significantly reduce look-up table size with respect to standard, unconstrained piecewise polynomial approximations, with negligible reduction in accuracy. The reduction of look-up table size improves performances in terms of area and speed. Implementations of linear and quadratic interpolators for the reciprocal function f(x)=1/x are presented and analyzed as an application example in the paper.