Valery Axelrad

Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC, alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more cost-effective application of RET.

Impact of subwavelength CD tolerance on device performance

We describe a new procedure of design qualification to ensure manufacturability of deep sub-wavelength circuits. The procedure is based on optical simulation of the layout, integrated with device simulation of the layout, integrated with device simulation to meet predefined conditions set forth by the layout control lines called tolerance contours, a new concept proposed in this work, are first defined for active devices based on the geometry-dependent, target MOSFET parameters, such as ION and IOFF and for interconnecting lines, based on the resolution of the etch process, misalignment and overlap or enclosure of metal and contact layers. Drawn geometries, OPC features, or exposure conditions are then adjusted such that the simulated silicon images would fall within the tolerance contours. The concept is demonstrated on SRAM cell shrink from 120 to 100 nm technology nodes.

Efficient computational techniques for aerial imaging simulation

We discuss computational techniques for calculating aerial image intensity distributions from large GDS II files recently implemented in Depict, a photolithography simulator for projection imaging, resist exposure, post-exposure bake and development. In particular, an algorithm for rapid and accurate evaluation of the mask Fourier transform over large domains containing non-uniformly positioned mask elements is implemented. By controlling aliasing errors within the context of a multiple level scheme, this algorithm renders feasible the simulation of aerial images across large portions of integrated circuits. The algorithm also allows overlapping phase mask elements obeying multiplicative transmission rules, and mask element merging. Accuracy for integration of the extended light source is also reported.

A novel design-process optimization technique based on self-consistent electrical performance evaluation

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. Process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive Design-for-Manufacturing (DFM) flow. Process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

Subwavelength lithography: an impact of photomask errors on circuit performance

The impact of photo mask manufacturing errors in the photolithography process and subsequently on the final device and test circuit (ring oscillator) performance are investigated. A statistical Monte Carlo process generates a population of normally distributed simulated photo mask errors during the reticle manufacturing process. Further steps predict how these photo mask errors impact printed poly gate patterns under different lithography conditions. Sensitivity analysis performed with the Sequoia Device Designer software tool identified the metal oxide semiconductor field effect transistor (MOSFET) channel length (Lpoly) as the most sensitive MOSFET parameter and an estimate of the distribution of device performance for realistic photo mask errors is made.

Improvement of lithographic performance and reduction of mask cost by simple OPC

An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be competitive to a solution by complicated source shape and mask pattern. This technology is applied to cut pattern of 1 dimensional GDR layout of 20nm node and below. The simulation under ArF single exposure shows 16nm node of metal layer and 12nm node of gate layer can be resolved with rectangle mask patterns. For both layers bright field exposure is used and experimentally positive and negative tone developments are applied for metal layer (island patterns) and gate layer (cut patterns) respectively. The integrated process through SADP, etching, and so on is shown. It is found that the simple pattern has lower MEEF than the complicated ones. Applying simple mask pattern MEEF can be suppressed to be 3~4 even at 16nm node. The SEM images of the masks with simple and complicated shapes show that it is difficult to reproduce the complicated pattern accurately. We prepared mask data with various complexities of patterns and evaluated the writing time of an up-to-date EB writer. The time depends on the shot counts and a typical OPC pattern takes 4 times longer time than rectangle pattern. Since the cost of writing time is around 20% of the entire cost, the saved cost from OPC pattern to rectangle pattern becomes 15%. Regarding advanced node of mask with more complicated pattern it takes further longer time and there is an impact on other technologies of inspection or process. So the saved cost becomes huge.

Design strategies for ESD protection in SOC

Design strategies for efficient ESD protection in system-on-chip (SOC) integrated circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed using physical mixed-mode circuit-device simulation, utilizing finite element models for MOSFETs.

Novel procedure for mask disposition using electrical signatures of mask defects

Inspection and repair are increasingly more important components of the mask building process. Mask writing complexity and time make it necessary to accept plates containing defects such as line protrusions, particles, or voids. These defects are identified by a number of inspection tools, which should make it possible to distinguish between killer and nuisance defects. In the most advanced defect printability studies, a 10 percent linewidth (CD) variation in critical areas across process window are used to evaluate defect severity. This emphasizes defect printability for manufacturing rather than product functionality. In this work, we propose a simulation procedure that goes one step further towards product yield, by evaluating the impact of mask defects on device parameters. It first defines silicon image, followed by the identification of defects that actually degrade device characteristics beyond the limits specified for the product. The procedure involves simulated transistor characteristics based on its geometries and models, with drive and leakage currents used as the qualifying parameters.

A novel procedure to evaluate design scalability based on device performance linked to photolithography data

We propose a novel procedure to evaluate design manufacturability based on simulated photoresist patterns followed by extraction of MOSFET geometry and VT distribution. We demonstrate the procedure on a SRAM cell, to optimize photolithography for technology shrink from 0.16 to 0.13 /spl mu/m.

Analysis of microlithography in an open-architecture TCAD system

The paper offers the results of investigations of forming the submicron topological structures of the `contact window-type by using only all-dry vacuum and plasmas technologies. Analysis is made of the relationship between lithographic and electric parameters of contact systems with micron-size features. A technological process of manufacturing a three-layer structure `metal-dielectric-metal by using the LVPL is developed to study electric characteristic of systems with micron and submicron contact windows. Analysis is made of the 0.5 - 1.0 micrometers to 0.5 - 0.3 micrometers . To form masks, use was made of vacuum resist 0.4 to 0.7 micrometers films deposited onto 0.29 micrometers thick silicon oxide layers on a silicon substrate. The resist was subjected to exposure with simultaneous development on a LVPL apparatus. An average of laser radiation power, a pulse repetition rate, a degree of vacuum were maintained constant, while a dose was varied by changing the exposure at E equals 1 J/cm2. Next plasmochemical etching of Al or silicon oxide was performed through a vacuum resist-mask.