Linard Karklin

Application of alternating phase-shifting masks to 140-nm gate patterning: II. Mask design and manufacturing tolerances

In this paper we present the results of experimental patterning 140 nm poly gates with double-exposure alternating phase-shifting masks (PSM) using a Nikon EX-1 (KrF, 0.42NA) stepper. We show that: systematic intrafield line width variations can be controlled within 10 nm (3(sigma) ), interfield variations across the wafer to within 6 nm (3(sigma) ), and total variation across the wafer held to within 15 nm (3(sigma) ), with a target k1 factor of k1 equals 0.237 (140 nm target gate lengths). We also present the results of studies addressing several issues related to the production application of alternating PSMs, including mask manufacturing tolerances and full chip PSM design capabilities. We show that, in comparison to conventional binary masks, alternating PSMs reduce the criticality of mask line width control and reduce the sensitivity to mask defects. Furthermore tolerance to PSM phase errors can be significantly improved by placing a chrome regulator between phase-shifters. Automatic, high-speed full chip design of alternating strong PSM is now possible.

Automatic defect severity scoring for 193-nm reticle defect inspection

Sub-wavelength lithography requires knowledgeable application of resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift mask (PSM). Use of RETs, in turn, requires that new photomask specifications and special requirements for mask defect printability be taken into consideration. This is especially true, as the photomasks critical dimensions become more aggressive (400 nm moving toward 300 nm). Traditionally, mask defect analysis and subsequent defect disposition has been accomplished by first performing automated reticle inspection, and then by visual inspection ultimately dependent on operator judgement. As the semiconductor industry moves to more challenging process generations this methodology is no longer viable for assessing the impact of a defect on the printed wafer. New techniques for more accurate, production-worthy defect printability analysis and defect disposition procedures are required. Developed at Numerical Technologies, Inc. is the Virtual StepperTM System that offers a fast, accurate software solution for defect printability analysis based on state-of- the-art lithography simulation techniques for advanced masks production using OPC and PSM. The newly developed Virtual Stepper System feature, Automatic Defect Severity Scoring (ADSS) provides fully automated and accurate defect impact analysis capability by calculating a consistent Defect Severity Score (DSS) for each defect detected by an inspection tool. DSS is an overall score that quantifies the impact of a given defect on surrounding features and can be used as a comprehensive indicator of defect printability. Taken into consideration, are not only printing defects, but defects which cause critical dimension (CD) errors altering a given process window.

Application of alternating phase-shifting masks to 140-nm gate patterning: linewidth control improvements and design optimization

In this paper we show that the problem of intrafield line width variations can be effectively solved through a novel application of alternating phase-shifting mask (PSM) technology. To illustrate its advantages, we applied this approach to produce 140 nm transistor gates using DUV (248 nm wavelength, KrF) lithography. We show that: systematic intrafield line width variations can be controlled to within 10 nm (3 (sigma) ), and variations across the wafer held to within 15 nm (3 (sigma) ), with a target k1 factor of K1 equals 0.237 (140 nm target gate lengths).

Lithography process calibration with applications in defect printability analysis

Lithography process simulation has proven to be a useful and effective tool for process characterization, namely, properly characterize critical dimension (CD) variations from the design that are caused by proximity effects and distortions introduced by the patterning tool, reticle, resist processing and etching. Accurate lithography process simulator further enables process engineers to automate the tasks of advanced mask design, verification and inspection that are used in deep-sub-micron semiconductor manufacturing. However, to get the most benefit from process simulations, we should properly calibrate the simulation model according to the process to be characterized. That is, given a representative set of CD measurements obtained from the process, we fine-tune the process model parameters so that the simulated/predicted CDs well match the measured CDs. By doing so, we can ensure to some extent that process simulations give sensible results to be used in the design analysis, verification and inspection applications. In this paper, we would like to demonstrate the possibility of obtaining an accurate process model for lithography process simulations via model calibration. We will also demonstrate the accuracy of calibrated process simulations by applying the calibrated model in mask defect printability analysis. For simplicity, the process model and the algorithms used in model calibration will not be discussed in this article but in our future publications. In Section 2, we present the characterization and calibration of a 0.18 micrometer DUV lithography process using positive chemically amplified resist (APEX-E) as an example. We describe the test pattern selections, the calibration process, and the performance of the calibrated model in terms of predicting the CD measurements given test patterns. In Section 3, we briefly describe the technology of defect printability analysis based on process simulations. We will demonstrate that with the help of calibrated process simulations, we can quite accurately predict the printabilities of various test defects.