Victor V. Boksha

A novel design-process optimization technique based on self-consistent electrical performance evaluation

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. Process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive Design-for-Manufacturing (DFM) flow. Process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

Model-based optical proximity correction including effects of photoresist processes

In this paper, a new automatic model-based Optical Proximity Correction (OPC) approach is reported. It combines a fast aerial image solver and a physically based empirical resist model. The fast aerial image calculation is achieved by using the algorithm of the coherent decomposition of the partially coherent optical systems. The first order resist model of Brunner is extended to accommodate intensity log- slope variations. The modified model can be calibrated by either experimental data or resist process simulations. In this paper, resist simulations using Depict are selected to fit the model parameters. Defocus effects in OPC are also discussed. A new scheme that combines edge biasing and the addition of sub-resolution features is shown to greatly improve the process latitude.

Advanced simulation techniques for thick photoresist lithography

A method has been developed that allows accurate simulation of pattern profiles in photoresist in excess of 10 micrometer thick. The method uses the DEPICTR photolithography simulator to model i-line exposure, bake and development of Shipley SJRR5740 thick film photoresists with an Ultratech 2244i Wafer StepperR. Kim model inputs were estimated from a family of development rate curves obtained by processing wafers with a range of expose energies for logarithmically increasing develop times and measuring thickness change as the develop process occurred. These results were compared with dissolution results obtained using a laser-based dissolution rate monitor. Uncertainties in the measured photoresist absorbence, photosensitivity and refractive index coefficients were estimated and their influence on the simulated results were considered. An optimization procedure and algorithm that allows quantitative comparison of experimental and simulated photoresist profiles is presented. Simulated photoresist profiles were compared with patterns obtained from processed wafers. As a further test of the models, pattern profiles were simulated for 2 micrometer spaces in 10 micrometer thick photoresist through focus. Experimental and simulated pattern profiles from a range of exposure doses were also compared.

Mask design rules (45 nm) : Time for standardization

Time-to-mask (ttm) has been growing exponentially in the subwavelength era with the increased application of advanced RETs (Resolution Enhancement Technology). Not only are a greater number of design/mask layers impacted but more-and-more layers also have more severe restrictions on critical dimension uniformity (CDU) despite operating at a very low k1 factors necessitating rigorous but practical tolerancing. Furthermore, designs are also more complex, may be built up from blocks spanning different design styles, and occupy increasingly-large Rayleigh field areas. Given these factors and scales, its no wonder that the cycle time for verification of a design following RET, is growing however it is doing so exponentially and that this is a critical factor impeding ttm. Until an unambiguously interprable and standard Mask Design Rule (MaskDR) set is created, neither the designer nor the mask supplier can reliably verify manufacturability of the mask for the simple reason that ambiguity and inter-rule conflict are at the source of the problem and that the problem increasingly requires cooperation spanning a large ecosystem of tool, IP, and mask suppliers all needing to essentially speak the same language. Since the 130 nm node, Texas Instruments has enforced a strict set of mask rule checks (MRCs) in their mask data preparation (MDP) flow based on MaskDRs negotiated with their mask suppliers. The purpose of this effort has been to provide an a-priori guarantee that the data shipped to the mask shop can be used to manufacture a mask reliably and with high yield both from a mask standpoint and from the silicon standpoint. As has been reported earlier, mask manufacturing rules are usually determined from assumed or experimentally acquired/validated mask-manufacturing limits. These rules are then applied during RET/MDP data treatment to guide and/or limit pattern correction strategies. With increasing RET and low-k1 lithography challenges, the importance of MRCs compounds. Furthermore, it will be necessary to comprehend certain MRC restrictions in the design flow as well as in the RET and MDP space. While mask tool manufacturers will need to be able specify tools specifications relevant to the MRCs for a particular mask shop flow, software tool suppliers, such as for RET, need to do so as well with tools which comprehend, check for, and enforce MRCs consistently. IDMs, foundaries, mask shops, EDA companies and tool suppliers will need a common language for the discussion on MaskDRs and MRCs in order to reach unambiguous convergence. Experience at Texas Instruments shows that accurate description, specification, and interpretation of MaskDRs and applying the associated MRCs is critical to a successful advanced mask technology strategy. This paper proposes the creation of a standard MaskDR lexicon. The goal of such a lexicon is the standardization of MaskDRs and their definitions such that interested parties from various mask-related disciplines can discuss, negotiate, specify, test and enforce MaskDRs unambiguously. We further propose that this standard be machine readable and directly usable without the necessity for intermediate interpretations. This lexicon would allow the designers, IDMs, foundaries, mask suppliers, and equipment suppliers to unambiguously negotiate and agree upon mask manufacturability requirements for their particular application.

Device and lithography contextual mask rule generation

Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs. In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test maks design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance. We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution ehancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.

Optimal proximity correction: application for flash memory design

Proximity Correction is the technology for which the most of IC manufacturers are committed already. The final intended result of correction is affected by many factors other than the optical characteristics of the mask-stepper system, such as photoresist exposure, post-exposure bake and development parameters, etch selectivity and anisotropy, and underlying topography. The most advanced industry and research groups already reported immediate need to consider wafer topography as one of the major components during a Proximity Correction procedure. In the present work we are discussing the corners rounding effect (which eventually cause electrical leakage) observed for the elements of Poly2 layer for a Flash Memory Design. It was found that the rounding originated by three- dimensional effects due to variation of photoresist thickness resulting from the non-planar substrate. Our major goal was to understand the reasons and correct corner rounding. As a result of this work highly effective layout correction methodology was demonstrated and manufacturable Depth Of Focus was achieved. Another purpose of the work was to demonstrate complete integration flow for a Flash Memory Design based on photolithography; deposition/etch; ion implantation/oxidation/diffusion; and device simulators.

Comparison of different optical proximity correction models with three-dimensional photolithography simulation over planar substrates

Different models for model-based Optical Proximity Correction have been recently developed for improving the printability of IC designs. Each model has its own area of application and it can be verified by experiments or by using a calibrated photoresist simulator that can predict 3D shapes with enough accuracy and acceptable performance. In this work we describe the use of 3D photoresist simulation for exposure, post-exposure bake and development on planar substrates to study the characteristics of different models for model-based OPC. We also introduce a new OPC tool that it is based on an automated procedure for layout modification and fast 3D simulation of exposure, PEB and development.

Cost and yield estimation in a virtual IC factory

A methodology to include cost and yield estimation in a comprehensive TCAD model of semiconductor processing is presented. The underlying idea is that a process recipe used to drive TCAD simulators contains a complete set of information about the process. If it is combined with empirical equipment data, a set of models can be constructed to describe cost as a function of the process recipe and equipment data. This paper presents a user-configurable cost modeling tool tightly integrated with TCAD simulators, enabling the user to study related and important questions of cost and yield not covered by traditional TCAD tools.

Dry patterning of resistive masks and topological structures

The development of dry resistive mask patterning process is the most complex point in practical application of vacuum small-operation cluster automated technologies of producing integrated circuits with submicron range size elements. The problem is successfully solved by small-operation laser vacuum projection lithography (LVPL). The equipment cluster for LVPL includes the installation for dry deposition of resist films on the substrate and the installation for its exposition-displaying. Organic materials are used as resists in such process. It was discovered that topological element formation in resist layers takes place mainly because of high speed thermal processes of resist material sublimation exposed by laser radiation surface parts.

Influence of adjustment accuracy on the image quality for laser cluster systems of microlithography

Aberration research in the optic system was conducted by finding possible angles between the axis of the illuminator and a lens on the basis of the analysis of intensity on the image plane. Intensity distribution was drawn after calculation of aberration deformations of the wave front. Quality of the image of three lines with crosscut size of 0.5, 1.0 and 3.0 micrometers on the margin of 5 X 5 mm field was investigated with the worse variant taken into account.