Vamsi Vankamamidi

A line-based parallel memory for QCA implementation

Quantum-dot cellular automata (QCA) has been widely advocated as a new device architecture for nanotechnology. Using QCA, the innovative design of digital systems can be achieved by exploiting the so-called capability of processing-in-wire, i.e., signal manipulation proceeds at the same time as propagation. QCA systems require low power together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the in-wire paradigm can be exploited for storage purposes. This paper proposes a novel parallel memory architecture for QCA implementation. This architecture is based on storing information on a QCA line by changing the direction of signal flow among three clocking zones. Timing of these zones requires two additional clocks to implement a four-step process for reading/writing data to the memory. Its operation has been verified by simulation. It is shown that the requirements for clocking, number of zones, as well as the underlying CMOS circuitry are significantly reduced compared with previous QCA parallel architectures.

A Serial Memory by Quantum-Dot Cellular Automata (QCA)

Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nanotechnology. QCA systems require extremely low power, together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the paradigm of memory-in-motion can be fully exploited. This paper proposes a novel serial memory architecture for QCA implementation. This architecture is based on utilizing new building blocks (referred to as tiles) in the storage and input/output circuitry of the memory. The QCA paradigm of memory-in-motion is accomplished using a novel arrangement in the storage loop and timing/clocking; a three-zone memory tile is proposed by which information is moved across a concatenation of tiles by utilizing a two-level clocking mechanism. Clocking zones are shared between memory cells and the length of the QCA line of a clocking zone is independent of the word size. QCA circuits for address decoding and input/output for simplification of the Read/Write operations are discussed in detail. An extensive comparison of the proposed architecture and previous QCA serial memories is pursued in terms of latency, timing, clocking requirements, and hardware complexity.

Clocking and Cell Placement for QCA

In this paper we propose a novel two-dimensional clocking and timing scheme for systems which permit a reduction in the longest line length in each clocking zone. The proposed clocking schemes utilize logic propagation techniques which have been developed for systolic arrays. Placement of QCA cells is modified to ensure correct signal generation and timing. The significant reduction in the longest line length permits a fast timing and efficient pipelining to occur, while guaranteeing kink-free behavior in switching.

Design of a QCA memory with parallel read/serial write

This paper presents a novel memory architecture for implementation by quantum-dot cellular automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.

Novel memory designs for QCA implementation

Quantum-dot cellular automata (QCA) provides a new functional paradigm for information processing and communication. The main feature of this technology is the so-called processing-in-wire mechanism by which data movement and manipulation are strictly integrated. In this context, the design of memory devices is particularly challenging and interesting because the conventional storage arrangements applicable to CMOS based memories cannot be applied and innovative approaches must be used. This paper analyzes state-of-the art designs for QCA memories and proposes three new architectures that improve over past approaches different figures of merit.

Analysis and Evaluations of Reliability of Reconfigurable FPGAs

Many techniques have been proposed in the technical literature for repairing FPGAs when affected by permanent faults. Almost all of these works exploit the dynamic reconfiguration capabilities of an FPGA where a subset of the available resources is used as spares for replacing the faulty ones. The choice of the best reconfiguration technique depends on both the required reliability and on the architecture of the chosen FPGA . This paper presents a survey of these techniques and explains how the architectural organization of the FPGA affects the choice of a reconfiguration strategy. Subsequently, a framework is proposed for these techniques by which a fair comparison among them can be assessed and evaluated with respect to reliability. A reliability evaluation is provided for different repair strategies. To provide a comparison between these techniques FPGAs of different size are taken into account. Also the relationship between the area overhead and the overall reliability has been investigated. Considerations about time to repair and feasibility of these techniques are provided. The ultimate goal of this paper is therefore to present a state-of-the-art repair techniques as applicable to FPGA and to establish their performance for reliability.

Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits

This paper analyzes the effect of random phase shifts in the underlying clock signals on the operation of several basic Quantum-dot Cellular Automata (QCA) building blocks. Such phase shifts can result from manufacturing variations or from uneven path lengths in the clocking network. We perform numerical simulations of basic building blocks using two different simulation engines available in the QCADesigner tool. We assume that the phase shifts are characterized by a Gaussian distribution with a mean value of

Design of defect tolerant tile-based QCA circuits

i \frac{\pi}{2}

Timing Verification of QCA Memory Architectures

, where i is the clock number and a standard deviation, σ, which is varied in each simulation. Our results indicate that the sensitivity of building blocks to phase shifts depends primarily on the layout while the reliability of all building blocks starts to drop once the standard deviation, σ exceeds 4°. A full adder was simulated to analyze the operation of a circuit featuring a combination of the building blocks considered here. Results are consistent with expectations and demonstrate that the carry output of the full adder is better able to withstand the phase shifts in the clocking network than the Sum output which features a larger combination of the simulated building blocks.

On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits

In this paper, a novel CAD-based approach is presented for defect tolerance of QCA circuits. This approach is based on using QCA tiles and provides defect tolerance at circuit level with, in most cases, no area overhead. A ranking methodology is introduced to determine the tile configurations and logic functions that are optimal for logic synthesis of QCA circuits. Simulations on benchmark circuits show that the proposed methodology provides significant improvements in defect tolerance compared with QCA gate-based designs.