Hamidreza Hashempour

Analysis and measurement of fault coverage in a combined ATE and BIST environment

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed; this approach is initially based on fault simulation using a small set of random vectors; an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.

ATE-amenable test data compression with no cyclic scan registers

This paper deals with a novel data compression technique for automatic test equipment (ATE). A new correlation extraction technique is presented which allows spanning of the compressed test data over the memory of multiple ATE channels. After reordering, vector processing is executed on a columnwise basis such that bits in the same position of all vectors are simultaneously provided to each pin of the head. Differentiation which is commonly used to extract correlation among vectors is not required in the proposed technique. Several ATE issues related to memory utilization, off-chip compression/decompression, decompression circuitry area overhead (inclusive of the area of the cyclic-scan-register, CSR), and entropy of test data (as figure of merit for correlation extraction) are analyzed. Experimental results for combinational and sequential benchmark circuits are presented to substantiate the validity of the proposed technique for an ATE environment.

Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs

Carbon nanotube field effect transistors (CNTFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. The core of a CNTFET is a carbon nanotube. Its conductance property is determined by the so-called chirality of the tube; chirality is difficult to control during manufacturing. This results in conducting (metallic) nanotubes and defective CNTFETs similar to stuck-on (SON or source-drain short) faults, as encountered in classical MOS devices. This paper studies this phenomenon by using layout information and presents modeling and detection methodologies for nano-scaled defects arising from the presence of metallic carbon nanotubes. For CNTFET-based circuits (e.g. intramolecular), these defects are analyzed using a traditional stuck-at fault model. This analysis is applicable to primitive and complex gates. Simulation results are presented for detecting modeled metallic nanotube faults in CNTFETs using a single stuck-at fault test set. A high coverage is achieved (~98%)

Application of arithmetic coding to compression of VLSI test data

This paper proposes arithmetic coding for application to data compression for VLSI testing. The use of arithmetic codes results in a codeword whose length is close to the optimal value (as predicted by entropy in information theory), thus achieving a higher compression. Previous techniques (such as those based on Huffman or Golomb coding) result in optimal codes for data sets in which the probability model of the symbols satisfies specific requirements. This paper shows empirically and analytically that Huffman and Golomb codes can result in a large difference between the bound established by the entropy and the attained compression; therefore, the worst-case difference is studied using information theory. Compression results for arithmetic coding are presented using ISCAS benchmark circuits; a practical integer implementation of arithmetic coding/decoding and an analysis of its deviation from the entropy bound are pursued. A software implementation is proposed using embedded DSP cores. In the experimental evaluation, fully specified test vectors and test cubes from two different ATPG programs are utilized. The implications of arithmetic coding on manufacturing test using an ATE are also investigated.

Error-resilient test data compression using Tunstall codes

This paper presents a novel technique for achieving error-resilience to bit-flips in compressed test data streams. Error-resilience is related to the capability of a test data stream (or sequence) to tolerate bit-flips which may occur in an automatic test equipment (ATE), either in the electronics components of the loadboard or in the high speed serial communication links between the user interface workstation and the head. Initially, it is shown that errors caused by bit-flips can seriously degrade test quality (as measured by the coverage), as such degradation is very significant for variable codeword techniques such as Huffman coding. To address this issue a variable-to-constant compression technique (namely Tunstall coding) is proposed. Using Tunstall coding and bit-padding to preserve vector boundaries, an error-resilient compression technique is proposed. This technique requires a simple algorithm for compression and its hardware for decompression is very small, while achieving a much higher error-resilience against bit-flips compared with previous techniques (albeit at a small reduction in compression). Simulation results on benchmark circuits are provided to substantiate the validity of this approach in an ATE environment.

Test time reduction in a manufacturing environment by combining BIST and ATE

This paper analyzes an environment which utilizes Built-In Self-Test (BIST) and Automatic Test Equipment (ATE), to reduce the overall time for manufacturing test of complex digital chips. This requires properly establishing the time to switch front BIST to ATE (referred to us switchover time), thus utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment we model fault coverage us a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed: this approach is initially bused on fault simulation using a small set of random patterns: art estimate of the so-called detection profile of the circuit under test is established us basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE us related testing processes.

Evaluation of Error-Resilience for Reliable Compression of Test Data

This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an automatic test equipment (ATE) to the device-under-test (DUT)). In an ATE, bit-flips may occur in either the electronics components of the loadboard, or the high speed serial communication links (between the user interface workstation and the head). It is shown that errors caused by bit-flips can seriously degrade the test quality (as measured by coverage) of the compressed data streams. The effects of bit-flips on compression are analyzed and various test data compression techniques are evaluated. It is shown that for benchmark circuits, coverage of test sets can be reduced by 10%-30%.

Analysis and evaluation of multisite testing for VLSI

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.

Evaluation of heuristic techniques for test vector ordering

Vector reordering is an essential task in testing VLSI systems because it affects this process from two perspectives: power consumption and correlation among data. The former feature is crucial and if not properly controlled during testing, may result in permanent failure of the device-under-test (DUT). The atter feature is a so important because correlation is captured by coding schemes to efficiently compress test data and ease memory requirements of Automatic-Test-Equipment (ATE),while reducing the volume of data and lowering the test application time. Reordering however is NP-complete. This paper presents an evaluation of different heuristic techniques for vector reordering using ISCAS85 and ISCAS89 benchmark circuits in terms of time and quality. For this application, it is shown that the best heuristic technique is not the famous Christofides or Lin-Kernighan, but the Multi-Fragment technique.

An Integrated Environment for Design Verification of ATE Systems

This paper deals with the verification of automatic test equipment (ATE) that is widely used for manufacturing testing of integrated circuits (ICs). Due to design complexity, manufacturers are facing substantial difficulties in verifying ATEs. Design flow and time execution of the verification process are severely limited when developing new hardware and software architectures for ATEs. We present a verification technique and its implementation, which has been put in practice in an ATE company. This technique reduces the time to detect errors in incorrect designs and provides an inexpensive and practical approach to verification of ATEs. It is based on establishing an integrated environment for the concurrent execution of diagnostic programs (which are developed for postmanufacturing ATE diagnosis) and the hardware- description-language models of the units of the ATE. Experimental results are provided to verify an application-specific IC chip for test pattern generation in the test head and software of the ATE.