Veeraiyah Thangasamy

A low power multiplexer based pass transistor logic full adder

In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits.

Digital-Controlled Multimode Multiband Power Amplifier with Multiple Gated Transistor

ABSTRACT Multimode multiband (MMMB) connectivity has become a de facto requirement for smartphones in order to accommodate the various different frequencies, bandwidths, output power, and modulation schemes. In this work, a two-stage single-chip MMMB power amplifier (PA) with multiple gated transistor technique has been designed to obtain dual-mode output power options, with its input matching and intermediate matching networks made tunable to enable switching of the PA output between low-band and high-band frequencies. In the low-band region, the PA offers 195 MHz of operating bandwidth starting from the frequency of 770 up to 965 MHz, covering the long term evolution (LTE) bands 5 and 8, with output saturated power of 27.3 dBm and peak power added efficiency (PAE) of 47.4%. In the high-band region, the PA has 900 MHz bandwidth starting from the frequency of 1.3 up to 2.2 GHz, covering the LTE bands 1, 2, and 3, with output saturated power of 27.9 dBm and peak PAE of 45.3%. The achieved ACPRs are −40 and −42 dBc in the low-band and high-band, respectively, which are well within the LTE linearity specifications. By using a low-cost CMOS process, the proposed MMMB PA has potential applications in the system-on-chip (SoC) integration of wireless transceiver.

Numerical analysis on prospects of high efficiency CdS/CdTe thin film solar cell

Photovoltaic (PV) energy is one of the significant renewable energies with free and permanent resource. Cadmium Telluride (CdTe) is from group II-VI of compound polycrystalline semiconductors. The CdTe solar cell material can be produced in thinness of film; hence, it is very appropriate for thin film solar cell industry production. The main purpose of this investigation is to model and analyze a prospect structure of thin film CdTe solar cell by AMPS-1D software. In this solar cell structure, Thin Oxide (SnO2) as front contact, Cadmium Sulfide (CdS) as window layer, CdTe as absorber layer and Molybdenum (Mo) as back contact are used respectively. In this paper, the carrier concentration changes, thicknesses effects, temperature stability and effect of two buffer layers of Zinc Stannate (Zn2SnO4) and Zinc Oxide (ZnO) on the CdTe solar cell output performance are investigated to obtain an optimum thin film structure of CdTe solar cell. This study aims to obtain the thickness of 1 μm for CdTe absorber layer. The conversion efficiency of the optimized structure of CdTe thin film solar cell (SnO2/CdS/CdTe/Mo) is up to 21.313% (VOC = 0.756 V, JSC = 34.282 mA/cm2 and FF = 0.822) with a thickness of 1.2 μm. Obviously, this structure is cost-efficient due to its thickness. Furthermore, temperature coefficient of the final proposed structure (ZnO, Zn2SnO4/SnO2/CdS/CdTe/Mo) is less than 0.031% /°K which shows a well stability at higher operating temperature of the proposed CdTe thin film solar cell. Therefore, this CdS/CdTe structure can be a prospect of thin film solar cell with high efficiency.

Multimode multiband power amplifier with tapped transformer for efficiency enhancement in low power mode

Multimode multiband connectivity has become a defacto requirement for smartphones with 3G WCDMA/4G LTE applications. In this research, a two-stage multimode multiband (MMMB) power amplifier (PA) with multiple gated transistor (MGTR) and configurable tapped transformer is designed and analysed in view of enhancing the efficiency in low power mode. The designed MMMB PA offers a 900MHz of operating bandwidth starting from the frequency of 1400MHz up to 2300MHz, covering 16 LTE FDD bands with peak output power of 27.8dBm and peak PAE of 31% in the high power mode. In low power mode, the PA offers the same bandwidth with peak output power of 25.5dBm and PAE of 30%. Use of the multiple gated transistor with tapped transformer for matching has increased the PAE in low power mode by 19% compared with that PAE in the high power mode.

Wireless power transfer with on-chip inductor and class-E power amplifier for implant medical device applications

The popular use of biomedical implants has been going on in numerous applications that include the use of pacemakers and emerging retina prostheses, together with brain-computer interfaces. Other popular uses include drug delivery and smart orthopaedic implants. The avoidance of batteries or piercing wirings has made the wireless powering of these implantable devices highly attractive. In this paper, a design of a class-E power amplifier which has inductive loading appropriate for implant application was made using 130nm Silterra CMOS process at 2.4V supply. A presentation of high-Q on-chip inductors is made as a way of improving the efficiency of the wireless power transfer (WPT) system at 37.5MHz industrial, scientific and medical (ISM) band. Wireless power transfer efficiency of 59-89% is obtained for distance variation up to 10mm of the implant coil from the transmit power coil. DC voltage of more 3V is obtained for distance up to 10mm of the implant coil; and the on-chip implant inductor measures a smaller size of 10mm×10mm making the design more suitable for the application of medical implant.