Zubaida Yusoff

Linearity improvement in RF power amplifier system using integrated Auxiliary Envelope Tracking system

A new technique called Auxiliary Envelope Tracking (AET) is proposed, which demonstrates substantial improvement in linearity of RF power amplifiers. A small amplitude envelope-tracking voltage is superimposed on the fixed DC bias of a specially designed 25W GaN HEMT Class AB RF power amplifier (RFPA). A large improvement in third-order intermodulation (IM3) distortion has been observed while maintaining low fifth-order intermodulation (IM5). The overall drain efficiency of the RFPA is also observed to improve, even when the power consumption of the envelope tracking generator is included. The AET concept uses a simple and easily integrated system that consists of an RFPA, a diplexer and an envelope amplifier.

Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) used in the design. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and output signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mum 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 mum x 116.16 mum. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking and low jitter properties.

A Highly Linear CMOS Down Conversion Double Balanced Mixer

This paper presents a high linearity CMOS down conversion double balanced mixer for IEEE802.11/g Wireless LAN application with 2.4 GHz operating frequency. In this Gilbert type mixer design, various high linearity techniques have been incorporated such as current-reuse bleeding technique, common gate transconductance amplifier configuration and tuned loads techniques. All these techniques were combined into a single design and the comparison of this proposed mixer with the recent literature shows significant improvement in linearity parameters such as intermodulation (IMR3), third-order input intercept point (IIP3) and 1dB compression point without degrading other important parameters. The mixer structure is designed using TSMC 0.25 mum standard CMOS technology and is simulated using EldoRF simulator from Mentor Graphics environment. The mixers simulated result shows the input intercept point (IIP3) of 12.810 dB, the intermodulation IMR3 of 129.816dB and the 1 dB compression point of 5.075 dB. The mixer operates at 1.8 V with 13.30 mW power consumption. Meanwhile, the measured conversion gain and noise figure of this double balanced mixer were -2.688 dB and 13.678 dB respectively.

A low power multiplexer based pass transistor logic full adder

In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits.

Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchis experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchis nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of Vth. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.

The benefit of GaN characteristics over LDMOS for linearity improvement using drain modulation in power amplifier system

This paper reports that significant linearity improvement can be obtained in gallium nitride (GaN) RF power amplifiers (RFPAs) in comparison to laterally diffused metal oxide semiconductor (LDMOS) RFPAs through the use of a modulated drain supply. It is shown that the gain characteristic of a GaN RFPA has significant variation with the drain bias voltage and this results in a 10–20dB reduction in intermodulation (IM) levels. The LDMOS RFPA was measured and the result showed that the gain of LDMOS did not change substantially with drain bias voltage. As a consequence, when the LDMOS RFPA is measured using modulated drain bias, the IM levels showed only a much smaller improvement. These results appear to indicate that GaN devices have an important advantage over LDMOS in linear RFPA applications.

Digital-Controlled Multimode Multiband Power Amplifier with Multiple Gated Transistor

ABSTRACT Multimode multiband (MMMB) connectivity has become a de facto requirement for smartphones in order to accommodate the various different frequencies, bandwidths, output power, and modulation schemes. In this work, a two-stage single-chip MMMB power amplifier (PA) with multiple gated transistor technique has been designed to obtain dual-mode output power options, with its input matching and intermediate matching networks made tunable to enable switching of the PA output between low-band and high-band frequencies. In the low-band region, the PA offers 195 MHz of operating bandwidth starting from the frequency of 770 up to 965 MHz, covering the long term evolution (LTE) bands 5 and 8, with output saturated power of 27.3 dBm and peak power added efficiency (PAE) of 47.4%. In the high-band region, the PA has 900 MHz bandwidth starting from the frequency of 1.3 up to 2.2 GHz, covering the LTE bands 1, 2, and 3, with output saturated power of 27.9 dBm and peak PAE of 45.3%. The achieved ACPRs are −40 and −42 dBc in the low-band and high-band, respectively, which are well within the LTE linearity specifications. By using a low-cost CMOS process, the proposed MMMB PA has potential applications in the system-on-chip (SoC) integration of wireless transceiver.

Multi-wavelength Brillouin-Erbium Fiber Laser Utilizing a Fiber Bragg Grating Filter with Intra-Cavity Pre-Amplified Brillouin Pump

In this paper, we demonstrate an efficient multi-wavelength Brillouin-erbium fiber laser with a pre-amplified Brillouin pump within a Fabry-Perot cavity. With the utilization of a fiber Bragg grating filter as one of the fiber loop mirrors, up to 25 stable Brillouin Stokes lines could be generated with channels spacing of 0.088 nm. The architecture of the design needs only 3 dBm of the Brillouin pump power and 90 mW of the 980 nm laser diode to produce the 25 maximum output channels.

Low Power Techniques for a Mixed-Signal Circuit

This paper presents analyses performed on design techniques implemented on a mixed-signal circuit with the goal of minimizing static and dynamic power consumptions. The concept of multi-Vdd and multi-Vth is implemented through design parameter manipulation hence not having to change or require expensive process. The techniques are applied on a digital circuit, a phase detector, as well as on an analog circuit, a voltage-controlled oscillator. The results suggest a potential reduction of 30% in total power consumption for a digital circuit and 55% for a power-hungry VCO circuit.

An 8-Gb/s Half-Rate Clock and Data Recovery Circuit

This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18 u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35 ps to 110 ps. While the data output jitter p-p is 4.6 ps and the clock jitter p-p is 6.6 ps. The power consumption is 55 mW from a 1.8 V voltage supply.