Noor Ain Kamsani

Combining process and statistical variability in the evaluation of the effectiveness of corners in digital circuit parametric yield analysis

This paper focuses on two main types of MOSFET variability - systematic (process) and statistical (random) variability and discusses the use of process corners as a measure of yield and circuit performance. We provide a methodology for performing large-scale statistical SPICE simulations as a means of evaluating the accuracy of corners in a system dominated by statistical variability and then expand the methodology to include both systematic and statistical variability within the same large-scale SPICE simulations. This large-scale statistical/systematic approach is compared to the “global + local” statistical corner approach, which consists of statistical simulations around the process corners. Finally 2D kernel density estimates are used to extract yield data from the statistical simulations to allow energy/delay/yield optimization to be performed. This in turn highlights the deficiencies of the statistical corner approach.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifiers performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifiers output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

A low power multiplexer based pass transistor logic full adder

In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10-18 J and its power consumption is 2.01μW. The proposed full adder is also capable to function at lower supply voltages of 0.4 V and 0.8 V without significant performance degradation. The proposed adder when cascaded in a 4-bit ripple carry adder configuration, its power, delay and PDP performance are better than the other adders making it suitable for larger arithmetic circuits.

Digital-Controlled Multimode Multiband Power Amplifier with Multiple Gated Transistor

ABSTRACT Multimode multiband (MMMB) connectivity has become a de facto requirement for smartphones in order to accommodate the various different frequencies, bandwidths, output power, and modulation schemes. In this work, a two-stage single-chip MMMB power amplifier (PA) with multiple gated transistor technique has been designed to obtain dual-mode output power options, with its input matching and intermediate matching networks made tunable to enable switching of the PA output between low-band and high-band frequencies. In the low-band region, the PA offers 195 MHz of operating bandwidth starting from the frequency of 770 up to 965 MHz, covering the long term evolution (LTE) bands 5 and 8, with output saturated power of 27.3 dBm and peak power added efficiency (PAE) of 47.4%. In the high-band region, the PA has 900 MHz bandwidth starting from the frequency of 1.3 up to 2.2 GHz, covering the LTE bands 1, 2, and 3, with output saturated power of 27.9 dBm and peak PAE of 45.3%. The achieved ACPRs are −40 and −42 dBc in the low-band and high-band, respectively, which are well within the LTE linearity specifications. By using a low-cost CMOS process, the proposed MMMB PA has potential applications in the system-on-chip (SoC) integration of wireless transceiver.

Dual control Direct Digital Synthesizer (DCDDS) for electronic testing and experimental work

Direct Digital Synthesizer (DDS) used for creating arbitrary waveforms from a single, fixed-frequency reference clock. Applications of DDS include: signal generation, local oscillators in communication systems, function generators, mixers, modulators, electronic sound synthesizers and as part of a digital phase-locked loop. In this paper, DDS is used as a function generator operated in a particular frequency bandwidth and it is to be used for testing and experimental work. This paper will presents a possible design for keypad and computer controlled DDS function generator namely Dual Control Direct Digital Synthesizer (DCDDS) which generate frequencies from 0 to 30MHz sine waveform. The amplitude selection is up to 10Vpp, and it is guaranteed to be accurate for frequencies range from 0 to 1MHz. The ability to accurately generate and control waveform of various frequencies, compactness and low cost are the main design consideration.

Impact of random dopant induced statistical variability on inverter switching trajectories and timing variability

In this paper we study the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of an inverter at the 45nm technology generation using statistical circuit simulation. The impact of the variability on switching trajectories and propagation delay are studied using an inverter chain with differing Fan-Out/Fan-In (FO/FI) ratios.

Multimode multiband power amplifier with tapped transformer for efficiency enhancement in low power mode

Multimode multiband connectivity has become a defacto requirement for smartphones with 3G WCDMA/4G LTE applications. In this research, a two-stage multimode multiband (MMMB) power amplifier (PA) with multiple gated transistor (MGTR) and configurable tapped transformer is designed and analysed in view of enhancing the efficiency in low power mode. The designed MMMB PA offers a 900MHz of operating bandwidth starting from the frequency of 1400MHz up to 2300MHz, covering 16 LTE FDD bands with peak output power of 27.8dBm and peak PAE of 31% in the high power mode. In low power mode, the PA offers the same bandwidth with peak output power of 25.5dBm and PAE of 30%. Use of the multiple gated transistor with tapped transformer for matching has increased the PAE in low power mode by 19% compared with that PAE in the high power mode.

Wireless power transfer with on-chip inductor and class-E power amplifier for implant medical device applications

The popular use of biomedical implants has been going on in numerous applications that include the use of pacemakers and emerging retina prostheses, together with brain-computer interfaces. Other popular uses include drug delivery and smart orthopaedic implants. The avoidance of batteries or piercing wirings has made the wireless powering of these implantable devices highly attractive. In this paper, a design of a class-E power amplifier which has inductive loading appropriate for implant application was made using 130nm Silterra CMOS process at 2.4V supply. A presentation of high-Q on-chip inductors is made as a way of improving the efficiency of the wireless power transfer (WPT) system at 37.5MHz industrial, scientific and medical (ISM) band. Wireless power transfer efficiency of 59-89% is obtained for distance variation up to 10mm of the implant coil from the transmit power coil. DC voltage of more 3V is obtained for distance up to 10mm of the implant coil; and the on-chip implant inductor measures a smaller size of 10mm×10mm making the design more suitable for the application of medical implant.

Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency

Dynamic Thermal Management (DTM) emerged as a solution to address the reliability challenges with thermal hotspots and unbalanced temperatures. DTM efficiency is highly affected by the accuracy of the temperature information presented to the DTM manager. This work aims to investigate the effect of inaccuracy caused by the deep sub-micron (DSM) noise during the transmission of temperature information to the manager on DTM efficiency. A simulation framework has been developed and results show up to 62% DTM performance degradation under DSM noise. The finding highlights the importance of further research in providing reliable on-chip data transmission in DTM application.

Analog IC test and product engineering curriculum for M

Production test is a significant driver of semiconductor manufacturing cost. Parallel with the advances of semiconductor fabrication, the need for a pool of talented product and test engineers is significantly increasing. This paper describes the academia-industries collaboration effort in developing an analogue electronic test and product engineering to boost-up technical competencies of electronic engineering graduates particularly in microelectronic major. The program has been successfully conducted at Universiti Putra Malaysia with strong support from Texas Instruments and Teradyne.