Veikko Porra

High-frequency periodic time-domain waveform measurement system

A system is presented for the accurate measurement of high-frequency periodic time-domain voltage and current waveforms of a nonlinear microwave device. The measurements are performed in the time domain using a high-speed sampling oscilloscope. The results are Fourier-transformed into the frequency domain for error correction and then back into the time domain. An error-correction algorithm is presented that makes it possible to obtain accurate waveforms in spite of nonideal system components. Practical difficulties in measurement-system characterization are also discussed. An accurate circuit model for the measurement fixture is developed and its element values are determined. Measurement results are given showing the waveforms in a microwave transistor operated in the nonlinear region. The errors caused by signal processing are discussed. >

A low-voltage, low-power CMOS fifth-order elliptic GM-C filter for baseband mobile, wireless communication

The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.

A QCIF Resolution Binary I/O CNN-UM Chip

In this paper is reported a Cellular Nonlinear Network Universal Machine realization where there are 176 × 144 active cells. The size of the network is the standardized QCIF video image format and the design is aimed to be used in segmenting video images in future video applications requiring very low bit-rate for image transmission. The achieved cell density is 3000 cells/mm2 with a 0.25 micron standard digital CMOS process. Different building blocks inside the cell are given in detail and also the other implemented circuitry is thoroughly discussed. The physical realization of the design is also reported.

VLSI implementation of a reconfigurable cellular neural network containing local logic (CNNL)

A new integrated circuit cellular neural network implementation having digitally or continuously selectable template coefficients is presented. Local logic and memory is added into each cell providing a simple dual computing structure (analog and digital). The variable-gain operational transconductance amplifier (OTA) is used as voltage controlled current sources to program the weighting factors of the template elements. A 4-by-4 CNN circuit is realized using the 2 mu m analog CMOS-process. The circuit with different template configurations has been simulated with HSPIC.<<ETX>>

Programmable analogue VLSI CNN chip with local digital logic

A new integrated circuit cellular neural network implementation with digitally or continuously selectable template coefficients is presented. Local logic and memory are added into each cell, providing a simple dual (analogue and digital) computing structure. Variable gain OTAs are used as the voltage-controlled current sources to programme the template element values. the cells have local switched feedback (both analogue and digital) to feed from the output to the input or state capacitor. Therefore this analogue array processor can be applied to solve problems with a sequence of different templates. A 4 × 4 CNN circuit is realized using the 2 μm analogue CMOS process.

Miniaturized artificial-transmission-line monolithic millimeter-wave frequency doubler

Millimeter-wave signals are typically generated by frequency multiplication in modern single-chip or multichip module (MCM) systems. Consequently, the multiplication efficiency, spurious rejection, and size of the frequency multiplier ultimately limit the integration level and cost of these systems. This paper points to the size reduction of millimeter-wave frequency doublers by evaluating artificial transmission lines (ATLs) as a means to minimize the size of the low-impedance shunt stubs. As a result, we developed a 40-GHz frequency doubler, which used only 0.6-mm/sup 2/ area on a monolithic microwave integrated circuit. Despite the area minimization, the doubler exhibited state-of-the-art conversion loss of 1 dB over 10% bandwidth and rejected the fundamental frequency signal by more than 20 dB over 25% bandwidth. Reported herein is the novel simulation of the frequency doubler with active harmonic loads. Included in this paper are theoretical evaluation and simulation of ATLs with models for lumped components and verification of the results by electromagnetic simulation. Due to the high efficiency, low area requirement, and over 20-dB rejection of the fundamental signal, this miniaturized ATL frequency doubler can be used as a building block in the generation of local-oscillator signals in single-chip and MCM millimeter-wave systems.

A low-voltage rail-to-rail CMOS V-I converter

This paper presents CMOS low-voltage rail to-rail voltage-to-current (V-I) converters which could be used as basic building blocks to construct low-voltage current-mode analog very large scale integration (VLSI) circuits. In the circuit, an n-type V-I converter cell is connected in parallel with its p-type counterpart to achieve common-mode rail to-rail operation. A linear differential relationship of the n-type V-I converter, or its p-type complement, is obtained using a new class-AB linearization technique. The constant transconductance value is obtained by manipulating the DC bias currents of n- and p-type V-I converter cells. The circuit can operate from rail to rail with a power supply of 3 V or less, depending on the VLSI technology and the DC bias current level.

Low phase noise signal generation circuits for 60 GHz wireless broadband system

Demand for large capacity and low installation costs explains the extensive use of millimeter wave frequencies in digital wireless broadband communications. In digital wireless systems, the achievable bit error rate is strongly dependent on low phase noise in millimeter wave signal sources. The low phase noise can be achieved with frequency multiplication of high performance microwave oscillators. This study aims to reduce the size of millimeter wave frequency doublers by evaluating the spiral transmission line transformer as a means to minimize the size of the balun. As a result we developed a millimeter wave frequency doubler, which used only 0.3 mm/sup 2/ area on MMIC. We also present theoretical evaluation and simulation of these novel balanced frequency doublers. Furthermore, a 60 GHz frequency doubler was designed to demonstrate the frequency doublers in a millimeter wave signal source with ultra low phase noise.

Low-voltage rail-to-rail CMOS differential difference amplifier

This paper introduces a low-voltage rail-to-rail wide range CMOS Differential Difference Amplifier (DDA). The input stage of this DDA comprises two rail-to-rail VI converters with large signal handling capability. In each V-I converter, an N-type converter cell is connected in parallel with its P-type counterpart cell in order to cover all the operating range of the common-mode input voltage. Its constant transconductance is achieved through the use of two maximum-current selecting circuits and an output substraction stage. Simulation results of the DDA with 3 V supply show that the DDA has a rail-to-rail constant input transconductance, a rail-to-rail output swing, 66 dB open-loop gain, and a 2.2 MHz bandwidth with C/sub L/=30 pF and R/sub L/=250 /spl Omega/. Low-voltage DDA-based circuits, such as an adder/substractor and an integrator, are given in this paper. They constitute basic blocks of modern low-voltage analog signal and information processing systems.

Micropower CMOS GM-C filters for speech signal processing

In this paper, CMOS implementations of two low-voltage, micropower 5th-order elliptic low-pass GM-C filters are presented. Both of the 5th-order elliptic low-pass GM-C filters operate at a supply voltage of 3 V. Their tunable cutoff frequencies are from 3 Hz to 600 Hz and from 140 Hz to 3.5 kHz, respectively. The Operational Transconductance Amplifier (OTA) in these GM-C filter design is implemented by a low-voltage voltage-to-current converter (V-I converter) working in the weak-inversion region. The transconductance can be tuned by DC currents or DC voltage. This V-I converter can also be used as a basic building block to construct low-voltage, micropower analog VLSI signal processing systems. These filters provide a practical means for implementing very large time constants on-chip allowing single-chip solutions at very low frequencies. They can be applied in speech processing systems and other very low frequency applications.