Kari Stadius

Analysis and Design of Passive Polyphase Filters

Passive RC polyphase filters (PPFs) are analyzed in detail in this paper. First, a method to calculate the output signals of an n-stage PPF is presented. As a result, all relevant properties of PPFs, such as amplitude and phase imbalance and loss, are calculated. The rules for optimal pole frequency planning to maximize the image-reject ratio provided by a PPF are given. The loss of PPF is divided into two factors, namely the intrinsic loss caused by the PPF itself and the loss caused by termination impedances. Termination impedances known a priori can be used to derive such component values, which minimize the overall loss. The effect of parasitic capacitance and component value deviation are analyzed and discussed. The method of feeding the input signal to the first PPF stage affects the mechanisms of the whole PPF. As a result, two slightly different PPF topologies can be distinguished, and they are separately analyzed and compared throughout this paper. A design example is given to demonstrate the developed design procedure.

Multitone Fast Frequency-Hopping Synthesizer for UWB Radio

A fast frequency-hopping six-band local oscillator signal generator is described in this paper. Targeted for a Wi-Media ultra-wideband radio transceiver, it offers operation in mandatory band group 1 and in extensional band group 3. The circuit entity consists of three parallel phase-locked loops (PLLs), each including two voltage-controlled oscillators, one per band group, and a signal multiplexer for fast frequency selection. A broadband poly-phase RC filter is used for in-phase/quadrature generation. Furthermore, the synthesizer generates the clock signal for analog-to-digital converters by mixing the signals from the first and third PLL. The circuit was fabricated in a 0.13- mum CMOS process and it consumes 32 mA from a 1.2-V supply. It achieves 2-ns frequency settling time with a 3-MHz hopping rate.

Active inductors for GaAs and bipolar technologies

Integrated high performance gallium arsenide and silicon active inductor configurations for microwave frequencies are examined in this article. The existing topologies are considered and a new aspect of comparing the performance of different topologies based on a more complete analysis is utilised. Drawbacks of GaAs technology in this particular case are recognised, while benefits attained by using bipolar technology are presented. A theoretical basis for designing bipolar inductors is examined. On the basis of these studies a new method for raising the Q-factor of an active inductor is found and applied to two novel GaAs Q-enhanced active inductors. New applications for active high-Q resonators are found and their realisation aspects are considered. Integrated test circuits have been designed, and the simulated and experimental results are presented.

Q-enhancing technique for high speed active inductors

Integrated active inductor configurations for RF frequencies are examined in this paper. A new aspect of comparing the performance of different topologies is used, and consequent differences between technologies are recognised. On the basis of these studies a new method for raising the Q-factor is presented and its applications considered.<<ETX>>

Monolithic active resonators for wireless applications

In this paper new tunable, monolithic active resonator topologies are presented. The circuits, based on the advances in GaAs MMIC active inductors, show stable, high-Q performance with large tunability and compact layout. The simulated results exceed significantly the properties of conventional varactor-tuned circuits. The new circuits are applied to active filters and proposed active resonator oscillators (ARO), which show great potential for wireless applications at the 2 GHz band.<<ETX>>

A 2.4-GHz low-power all-digital phase-locked loop

This paper presents an all-digital phase-locked loop (ADPLL) for the 2.4-GHz ISM band frequency synthesis. The ADPLL is built around a digitally controlled LC oscillator. In the feedback path, a high-speed topology is employed for the variable phase accumulator to count full cycles of the RF output. A simple technique based on a short delay line in the reference signal path allows the time-to-digital converter core to operate at a low duty cycle with about 95% reduction of its average power consumption. To allow direct frequency modulation, the ADPLL incorporates a two-point modulation scheme with an adaptive gain calibration. Fabricated in a 65-nm CMOS, the ADPLL has an active area of 0.24 mm2. Measured phase noise at 1-MHz offset is -120 dBc/Hz with a power consumption of 12 mW, and -112 dBc with power consumption lowered to 8 mW. The integrated phase noise of the ADPLL is measured to be 1.7° rms.

Wide-tuning-range dual-VCOs for cable modem receivers

A double-conversion receiver for cable modem applications requires a wide-tuning-range VCO with low phase noise characteristics for the first LO generation. Achieving simultaneously low phase noise and large tuning range from a monolithic VCO is an exceptionally challenging task. The design aspects of wideband monolithic LC-VCO are tackled in this paper with the boundaries set by a 0.9-/spl mu/m SiGe HBT technology. Two dual-VCO implementations are presented and a method for buffering the VCO signal without loading the LC-resonator is proposed. Both simulation and experimental results are given.

Monolithic tunable capacitors for RF applications

Passive and active tunable capacitors for RF applications are discussed and compared in this paper. In silicon IC technologies passive tunable capacitors are either based on the p-n junction or the metal-semiconductor junction, i.e. the MOS-structure. Active capacitors discussed in this paper are based on the Miller effect or on the current steering principle (Gilbert cell). Modeling issues are discussed and measurement results presented for the passive structures. For active circuits the comparison is based on simulations and experimental results obtained from VCO circuits.

A WiMedia UWB receiver with a synthesizer

This paper describes a direct-conversion receiver for WiMedia UWB applications. The receiver consists of separate BG1 and BG3 LNAs including a 2.4-GHz notch filter, quadrature mixers, a base-band gm-C low-pass filter with variable gain, and a fast-hopping synthesizer. The UWB receiver is targeted for a mobile handset and therefore special emphasis has been placed on the reduction of interferers. The receiver achieves 60-dB gain, noise figure less than 6.2 dB, LO settling time of less than 3 ns and DC current consumption of 137 mA from a 1.2-V supply for BG1 operation mode. The chip was fabricated using 65-nm standard CMOS process.

A low-power wide-band digital frequency synthesizer for cognitive radio sensor units

This paper presents the design of a wide-band digital frequency synthesizer for cognitive radio sensor units. It is based on an all-digital phase-locked loop, and employs a digitally controlled ring oscillator with an LC tank introduced to extend tuning range and reduce power dissipation. Adaptive frequency calibration based on binary search is used for fast frequency settling. Fabricated in a 65-nm CMOS, the frequency synthesizer has an active area of 0.3 mm2 and achieves a frequency tuning range of 2.7 to 6.1 GHz, with power consumption less than 22 mW from a 1.2-V supply. Measured phase noise at 6-GHz frequency is −92 dBc/Hz at 1-MHz offset.