Vickram Vathulya

Characterization of inversion and accumulation layer electron transport in 4H and 6H-SiC MOSFETs on implanted P-type regions

The silicon carbide double implanted vertical MOSFET (SiC DIMOS) is a promising candidate for high power switching applications due to the absence of high electric field corners and compatibility with planar IC technology. In this work, we report on the channel mobility behavior in 4H and 6H-SiC MOSFETs fabricated with a low thermal budget process sequence, on implanted p-type regions which mirror the lateral carrier transport region in the DIMOS device. Channel mobilities are higher by an order of magnitude in 6H-SiC compared to 4H-SiC MOSFETs suggesting the 6H-SiC polytype is better suited for fabricating the DIMOS structure in spite of the superior vertical bulk conduction in 4H-SiC. Moreover, channel mobility on accumulated surfaces is higher than values obtained on inverted surfaces. A strong correlation between the observed threshold voltages and channel mobilities is consistently explained by a modified MOSFET conductance formulation in the presence of slowly decaying bandtail states toward the SiC band edges.

High density capacitance structures in submicron CMOS for low power RF applications

This paper presents four novel interconnect based capacitors with 2 to 3 times the capacitance density of a conventional metal sandwich capacitor and with self-resonant frequencies above 20 GHz, suitable for low power RF applications. Unlike the conventional capacitor, the capacitance density of these structures increases with the scaling of the technology. The structures have been fabricated in both 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies, measured and an equivalent circuit presented.