Vicky Yang

Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers

GaAs/AlxGa(1−x)As quantum well lasers have been demonstrated via organometallic chemical vapor deposition on relaxed graded Ge/GexSi(1−x) virtual substrates on Si. A number of GaAs/Ge/Si integration issues including Ge autodoping behavior in GaAs, reduced critical thickness due to thermal expansion mismatch, and complications with mirror facet cleaving have been overcome. Despite unoptimized laser structures with high series resistance and large threshold current densities, surface threading dislocation densities for GaAs/AlGaAs lasers on Si substrates as low as 2×106 cm−2 permitted continuous room-temperature lasing at a wavelength of 858 nm. The laser structures are uncoated edge-emitting broad-area devices with differential quantum efficiencies of 0.24 and threshold current densities of 577 A/cm2. Identical devices grown on commercial GaAs substrates showed similar behavior. This comparative data agrees with previous measurements of near-bulk minority carrier lifetimes in GaAs grown on Ge/GeSi/Si subst...

Dislocations in Relaxed SiGe/Si Heterostructures

Recent advances in the understanding and control of threading dislocations in substantially relaxed SiGe buffer layers on Si are presented. A model for threading dislocation flow in relaxed graded SiGe buffers is used to determine the potential lower limit of threading dislocation density in relaxed SiGe buffers. Greater densities than expected from the model are seen in relaxed graded alloys with final concentrations greater than 50%. We show that the culprits of the higher threading dislocation density are threading dislocation pile-ups. Observation of early development of pile-ups confirms that inhomogeneous misfit dislocation densities in the graded buffer form regions of more severe crosshatch on the surface that impede dislocation flow. By using chemomechanical planarization (CMP), deleterious pile-up formation can be avoided, and previously formed pile-ups can be destroyed by regrowth of a graded layer. Experiments with CMP and regrowth of graded layers suggest that dislocation annihilation can be effective at reducing threading dislocation densities to densities of the order expected by the model. High quality Ge on Si layers created with the CMP process were used as templates to grow high quality GaAs on Si with strong room temperature photoluminescence and record minority carrier lifetime.

Crack formation in GaAs heteroepitaxial films on Si and SiGe virtual substrates

We have determined the critical cracking thickness, or the thickness beyond which crack formation is favored, in GaAs films grown on Si and SiGe virtual substrates analytically and experimentally. The analytical model predicts a critical cracking thickness proportional to the biaxial modulus and the crack resistance of the GaAs film, and inversely proportional to the square of the thermal stress and a nondimensional crack resistance number Z. This Z number is determined by the mechanical properties of the GaAs film for a system without substrate damage, and is also determined by the mechanical properties of the substrate for a system with substrate damage. The experimentally determined critical thicknesses were in general greater than the analytically derived values due to the kinetic barriers to crack nucleation, which were not taken into consideration in the models. In addition, we have observed an asymmetric crack array formation, where arrays running in the 〈110〉 substrate off-cut direction are favore...

Graded InxGa1−xAs/GaAs 1.3 μm wavelength light emitting diode structures grown with molecular beam epitaxy

In this study 1.1–1.3 μm wavelength light emitting diode (LED) structures with InxGa1−xAs compositionally graded buffers were grown on GaAs substrates with molecular beam epitaxy and characterized using microstructure and discrete device characterization techniques. The growth temperature and design of the graded buffer greatly affect the luminescence properties of the active device region above the graded buffer. These effects were most prominent in LED structures which incorporated a quantum well in the active device region. In quantum well devices, bright luminescent bands in the 〈110〉 directions are revealed under cathodoluminescence investigation and the number of bands and their intensity depend on grading rate. This study shows that a high threading dislocation density generated at or above the quantum well region has an adverse effect on the I–V characteristics of the diodes, but did not hinder luminescence from the quantum well LEDs.

Comparison of luminescent efficiency of InGaAs quantum well structures grown on Si, GaAs, Ge, and SiGe virtual substrate

In order to study the luminescent efficiency of InGaAs quantum wells on Si via SiGe interlayers, identical In0.2Ga0.8As quantum well structures with GaAs and Al0.25Ga0.75As cladding layers were grown on several substrates by an atmospheric metalorganic vapor deposition system. The substrates used include GaAs, Si, Ge, and SiGe virtual substrates. The SiGe virtual substrates were graded from Si substrates to 100% Ge content. Because of the small lattice mismatch between GaAs and Ge (0.07%), high-quality GaAs-based thin films with threading dislocation densities <3×106 cm−2 were realized on these SiGe substrates. Quantitative cathodoluminescence was used to compare the luminescent efficiency of the quantum well structure on the different substrates and cross-sectional transmission electron microscopy was used to characterize dislocation densities. Our results show that the InGaAs quantum wells grown on the GaAs substrates have the highest luminescent efficiencies due to the lowest dislocation densities. Int...

Monolithic integration of III-V materials and devices on silicon

The realization of monolithic optical interconnects by integration of III-V materials with conventional Si circuitry has long been hindered by materials incompatibilities (i.e. lattice mismatch and heterovalent interface) and practical processing constraints. We have demonstrated successful integration of hetero-epitaxially grown InGaAs/Si diodes with an n-well CMOS process on (001) Si offcut 6 degrees towards [110]. The In0.15Ga0.85As/InxGa1- xAs/GaAs/Si diodes were grown by atmospheric pressure organo-metallic chemical vapor deposition (OMCVD) and features a room temperature R0A product of 20,000 ohm-cm2. No degradation of PMOS or NMOS transistor characteristics was detected upon integration of the III-V devices. Further improvement of III-V/Si device characteristics are anticipated in future efforts by incorporating relaxed, compositionally- graded Ge/GexSi1-x/Si with low threading dislocation densities (approximately 2 X 106/cm2) to bridge the gap in lattice constants between Si and GaAs. Recent progress towards this end includes the suppression of antiphase disorder during GaAs growth on Ge/GexSi1-x/Si by OMCVD and strong room temperature photoluminescence from In0.20Ga0.80As QW test structures on GaAs/GexSi1- x/Si at 920 nm.

Strategies For Direct Monolithic Integration of AlxGa(1-x)As/InxGa(1-x)As LEDS and Lasers On Ge/GeSi/Si Substrates Via Relaxed Graded GexSi(1-x) Buffer Layers

Abstract : Al(x)Ga(1-x)As/GaAs quantum well lasers have been demonstrated via organometallic chemical vapor deposition (OMCVD) on relaxed graded Ge/Ge(x)Si(1-x) virtual substrates on Si. Despite Un-optimized laser structures with high series resistance and large threshold current densities, surface threading dislocation densities as low as 2 x 10(exp 6)/sq cm enabled cw room-temperature lasing at a wavelength of 858 nm. The laser structures are oxide-stripe gain-guided devices with differential quantum efficiencies of 0.16 and threshold current densities of 1550A/sq cm. Identical devices grown on commercial GaAs substrates showed differential quantum efficiencies of 0.14 and threshold current densities of 1700A/sq cm. This comparative data agrees with our previous measurements of near-bulk minority carrier lifetimes in GaAs grown on Ge/GeSi/Si substrates. A number of GaAs/Ge/Si integration issues including thermal expansion mismatch and Ge autodoping behavior in GaAs were overcome.