Ángel Rodríguez-Vázquez

Nonlinear switched capacitor 'neural' networks for optimization problems

A systematic approach is presented for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques. The method is based on formulating a dynamic gradient system whose state evolves in time toward the solution point of the corresponding programming problem. A neuron cell for the linear and the quadratic problem suitable for monolithic implementation is introduced. The design of this neuron and its corresponding synapses using SC techniques is considered in detail. An SC circuit architecture based on a reduced set of basic building blocks with high modularity is presented. Simulation results using a mixed-mode simulator (DIANA) and experimental results from breadboard prototypes are included, illustrating the validity of the proposed techniques. >

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs

Today, with 0.18-/spl mu/m technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-/spl mu/m technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-/spl mu/m standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3/spl times/3 neighborhoods in less than 1.5 /spl mu/s, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 /spl mu/s, and CNN-like temporal evolutions with a time constant of about 0.5 /spl mu/s. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks

A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

A 0.8-/spl mu/m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DACs) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-/spl mu/m single-poly double-metal technology and features 2-/spl mu/s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations.

Operational transconductance amplifier-based nonlinear function syntheses

It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be efficiently used for programmable nonlinear continuous-time function synthesis. Two efficient nonlinear function synthesis approaches are presented. The first approach is a rational approximation, and the second is a piecewise-linear approach. Test circuits have been fabricated using a 3- mu m p-well CMOS process. The flexibility of the designed and tested circuits was confirmed. >

A CNN universal chip in CMOS technology

This paper describes the design of a programmable cellular neural network (CNN) chip with added functionalities similar to those of the CNN universal machine. The prototype contains 1024 cells and has been designed in a 1.0 μm, n-well CMOS technology. Careful selection of the topology and design parameters has resulted in a cell density of 31 cells mm -2 and around 7-8 bits accuracy in the weight values. Adaptive techniques have been employed to ensure accurate external control and system robustness against process parameter variations.

On the design of voltage-controlled sinusoidal oscillators using OTAs

A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTAs) and capacitors is discussed. Two classical oscillator models, i.e. quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA, and this makes the structures well-suited for building voltage controlled oscillators (VCOs). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented. The circuits are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes showing the potential of OTA-based oscillators for high-frequency VCO operation are included. >

A VLSI‐oriented continuous‐time CNN model

This paper presents an analysis of the stability and convergence properties of the full signal range (FSR) CNN model. These properties are demonstrated to be similar to those of the Chua-Yang model and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model the dynamic range of the cell state variables equals the dynamic range of the cell output variables and is invariant with the application. This feature results in simpler circuit implementations, thus allowing higher cell densities and improving the robustness of CNN integrated circuits. The FSR CNN model is particularly well suited for programmable CNN integrated circuits.

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.

A CMOS implementation of FitzHugh-Nagumo neuron model

A CMOS circuit is proposed that emulates FitzHugh-Nagumos differential equations using OTAs, diode connected MOSFETs and capacitors. These equations model the fundamental behavior of biological neuron cells. Fitz-Hugh-Nagumos model is characterized by two threshold values. If the input to the neuron is between the two thresholds the output yields a sequence of firing pulses, if the input is outside this range, no output is observed. The resulting circuit due to the (voltage) programmability of the OTA allows one to easily vary parameters. Thus a large family of solutions can be obtained including the Van der Pols equation. Experimental results from a CMOS prototype are given that show the suitability of the technique used, and their potential for biological CMOS system emulation.