Vidya Kaushik

The electronic conduction mechanism in barium strontium titanate thin films

In the literature, the Schottky emission equation is widely used to describe the conduction mechanism in perovskite-type titanate thin films. Though the equation provides a good fit to the leakage current data, the extracted values of the Richardson and dielectric constants are inconsistent with their experimental values. In this work, a modified Schottky equation is applied. This equation resolves the difficulties associated with the standard Schottky equation. Also, the electronic mobility in thin films of barium strontium titanate is reported.

Estimation of fixed charge densities in hafnium-silicate gate dielectrics

In this paper, an effective technique and methodology for the estimation of fixed charge components in high-k stacks was demonstrated by varying both the SiO2 and high-k dielectric thicknesses. The SiO2 thickness was scaled on a single wafer by uniformly changing the etch time of a thermally grown SiO2 layer across the wafer. This minimized wafer-to-wafer variations and enables acquisition of statistically significant datasets. Layers with different thickness of both the nitrided and non-nitrided hafnium-silicate layers were then grown on these wafers to estimate all the interfacial and bulk charge components. The reproducibility and validity of this technique were demonstrated, and this method was used to compare the fixed charge levels in Hf-silicates (HfSiO) and nitrided-Hf-silicate (HfSiON) layers

(Ba,Sr)TiO3 thin films with conducting perovskite electrodes for dynamic random access memory applications

Interfaces and hence electrodes determine the performance of (Ba,Sr)TiO3 (BST) capacitors for ultralarge scale integration dynamic random access memories. Electrode materials forming a rectifying contact on BST drastically reduce the dielectric constant and hence the capacitance and charge storage density of the capacitor, when the dielectric thickness is reduced. This can limit the role of Pt as an electrode material for gigabit dynamic random access memories (DRAM). The conducting oxide, La0.5Sr0.5CoO3 (LSCO) with its perovskite structure, has structural and chemical compatibility with BST. Our results in LSCO/BST/LSCO capacitor show that the mechanism of conduction is not interface limited but predominantly bulk limited. A 75 nm BST film with LSCO electrodes shows a leakage current density of 1×10−7 A/cm2 at 1 V, 85 °C. The dielectric constant at 1 V, 105 Hz is 350, making LSCO a potential contact electrode for DRAM memories.

Investigation of hydrogen induced changes in SrBi2Ta2O9 ferroelectric films

The effect of hydrogen on strontium bismuth tantalate (SrBi2Ta2O9; SBT) ferroelectric capacitors is investigated. Using several analytical techniques such as x-ray diffraction, electron diffraction, Auger electron, scanning and transmission electron microscopies, the structural and compositional changes in the ferroelectric film are studied as a function of annealing gas and temperature. The mechanism for hydrogen induced damage to the capacitor is identified. Measurements show that the hydrogen induces both structural and compositional changes in the ferroelectric film. Hydrogen reacts with the bismuth oxide to form bismuth and the reduced bismuth diffuses out of the SBT film causing the electrodes to peel.

Interface characterization of high-quality SrTiO3 thin films on Si(100) substrates grown by molecular beam epitaxy

Single-crystal SrTiO3 has been grown on Si(100) using molecular beam epitaxy (MBE). The growth conditions, especially at the initial stage of nucleation, have a great impact on the SrTiO3/Si interface. A regrowth of an amorphous interfacial layer as thick as 23 A has been observed and identified as a form of SiOx. This is a direct result of an internal oxidation during the growth of the STO film due to the oxygen diffusion and reaction with the silicon substrate at the interface. The optimization of the deposition process in terms of growth temperature and oxygen partial pressure has led to an interfacial layer as thin as 11 A. Metal oxide semiconductor (MOS) capacitors with an equivalent oxide thickness tox of 12 A and a leakage current of 2×10−4 A/cm2 have been obtained for a 50 A SrTiO3.

Determination of effects of deposition and anneal properties for tetranitratotitanium deposited TiO2 dielectrics

Carbon and hydrogen free tetranitratotitanium was synthesized, which is believed to thermally decomposed primarily as: Ti(NO3)4→TiO2+4NO2+O2. The by-products of the thermal decomposition of tetranitratotitanium, which include NO2 and O2, may possibly provide a robust ultrathin tunnel interfacial layer. Due to the hydrogen free nature of thermolysis, N2O may form an oxynitride layer which has been shown to produce thermal oxynitrides with higher quality than NH3-based nitride oxides. Unlike titanium tetrakis isopropoxide (TTIP) deposited films, the interface state density more closely follows the “U” shape characteristic of conventional thermal SiO2/Si interfaces. The integrated interface state density is considerably less for the film annealed at higher temperature, which should produce considerably higher inversion layer mobilities. This improvement of the interface, compared to TTIP deposited films, is believed to be due to the elimination of water vapor from the deposition ambient.

Porous Silicon Formation in N−/N+/N− Doped Structures

This paper examines how dopant profile and anodization conditions affect the formation of buried porous silicon layers in n{sup {minus}}/n{sup +}/n{sup {minus}} doped wafers. Wafers with peak n{sup +} donor concentration {le}10{sup 18}/cm{sup 3} exhibit stray dendritic pores propagating from the n{sup +} layer into the n{sup {minus}} layers. depending on the anodization conditions these larger diameter dendritic pores can even penetrate the entire upper n{sup {minus}} layer, making it unusable for silicon-on-insulator device applications. Lower anodization voltages produce shorter dendrite lengths. Wafers with peak n{sup +} donor concentration {ge}3 {times} 10{sup 18}/cm{sup 3} exhibit negligible stray dendritic pores. In these wafers the buried porous silicon layer is confined only to areas with doping level {ge}1-2 {times} 10{sup 17}/cm{sup 3}. These results should help in optimizing n{sup {minus}}/n{sup +}/n{sup {minus}} doping profiles and anodization conditions for silicon-on-insulator device applications.

Device performance of transistors with high-/spl kappa/ dielectrics using cross-wafer-scaled interface-layer thickness

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO/sub 2/ interface layer between a silicon substrate and high-/spl kappa/ dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO/sub 2/ interface. This technique provides a powerful tool in examining the effect of the process variations on device performance.

Work function of Ni3Si2 on HfSixOy and SiO2 and its implication for Ni fully silicided gate applications

The effective work function (WF) of Ni3Si2 was evaluated on HfSixOy and SiO2 dielectrics. Ni3Si2 forms, in thin film Ni–Si diffusion couples with Ni to Si composition ratios between 1 and 2, after formation of a Ni2Si∕NiSi stack and by its reaction at moderate thermal budgets (comparable to those used in back end processing of complementary metal-oxide-semiconductor circuits). Ni3Si2 formation limits, on the Ni-rich side, the process window for NiSi fully silicided (FUSI) gates (NiSi at interface with dielectric) to reacted Ni–Si ratios <1.5. The WF of Ni3Si2 was found to have similar values and behavior to that of NiSi, both on SiO2 (showing similar modulation with dopants) and on HfSixOy, in contrast to Ni-richer silicides such as Ni2Si and Ni31Si12 which do not exhibit significant WF modulation with dopants on SiO2 and have considerably higher WF on HfSixOy. This suggests that the chemistry and structure of the original NiSi/dielectric interface are not modified significantly by the subsequent growth o...

Device characteristics of crystalline epitaxial oxides on silicon

There is an extensive effort in the transistor industry to develop an alternative high-k gate dielectric to replace SiO/sub 2/ due to tunneling limits. We have investigated the potential of crystalline perovskite oxides (SrTiO/sub 3/ or STO) grown epitaxially over Si as a gate dielectric. Transmission electron microscopy images show that these epitaxial STO films have an interfacial amorphous layer <10 /spl Aring/ thick, that is mostly SiO/sub 2/. Using tantalum nitride (TaN) as a gate electrode, capacitors and MOSFETs were fabricated. Films with an equivalent oxide thickness (EOT) of 9 /spl Aring/ were achieved from a 100 /spl Aring/ STO layer yielding a dielectric constant of /spl sim/160. Measurements on n- and p-channel MOSFETs show leakage currents at /spl plusmn/1 V beyond inversion of 15 mA/cm/sup 2/ and 25 mA cm/sup 2/ respectively. Drive currents of 245 and 20 /spl mu/A//spl mu/m were realized for n- and p-channel devices. Calculated field mobilities were 221 cm/sup 2//V-sec for electrons and 62 cm/sup 2//V-s for holes. The use of a gate stack that has a high-k material (STO) over a low-k material (SiO/sub 2/) may have some potential advantages over a single medium-k layer.