Barry O'Sullivan

Ubiquitous relaxation in BTI stressing—New evaluation and insights

The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are discussed in detail for pFET with SiON dielectric subjected to NBTI stress. Based on similarities with dielectric relaxation, a physical picture and an equivalent circuit are proposed.

Estimation of fixed charge densities in hafnium-silicate gate dielectrics

In this paper, an effective technique and methodology for the estimation of fixed charge components in high-k stacks was demonstrated by varying both the SiO2 and high-k dielectric thicknesses. The SiO2 thickness was scaled on a single wafer by uniformly changing the etch time of a thermally grown SiO2 layer across the wafer. This minimized wafer-to-wafer variations and enables acquisition of statistically significant datasets. Layers with different thickness of both the nitrided and non-nitrided hafnium-silicate layers were then grown on these wafers to estimate all the interfacial and bulk charge components. The reproducibility and validity of this technique were demonstrated, and this method was used to compare the fixed charge levels in Hf-silicates (HfSiO) and nitrided-Hf-silicate (HfSiON) layers

Analysis of Pb centers at the Si(111)/SiO2 interface following rapid thermal annealing

In this work, an experimental study of defects at the Si(111)/SiO2 interface following rapid thermal annealing (RTA) in a nitrogen ambient at 1040 °C is presented. From a combined analysis using electron spin resonance and quasistatic capacitance–voltage characterization, the dominant defects observed at the Si(111)/SiO2 interface following an inert ambient RTA process are identified unequivocally as the Pb signal (interfacial Si3≡Si⋅) for the oxidized Si(111) orientation. Furthermore, the Pb density inferred from electron spin resonance (7.8±1)×1012 cm−2, is in good agreement with the electrically active interface state density (6.7±1.7)×1012 cm−2 determined from analysis of the quasistatic capacitance–voltage response.

Low V T CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

Device performance of transistors with high-/spl kappa/ dielectrics using cross-wafer-scaled interface-layer thickness

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5-nm SiO/sub 2/ interface layer between a silicon substrate and high-/spl kappa/ dielectric, on a single wafer. The transistor results are promising with good mobility values and drive current. The slant-etching process has no detrimental effect on the electrical characteristics of the Si/SiO/sub 2/ interface. This technique provides a powerful tool in examining the effect of the process variations on device performance.

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An Lgmin reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (RSD) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering the laser power and optimizing the nitrogen and fluorine profile. This minimizes the increase of Si dangling bonds at the SiON/Si interface and the oxide fixed charges, generated by the thermo-mechanical stress (TMS) during the LA fast thermal gradient. The full potential of LA is demonstrated by skipping the RTA. An Lgmin gain of 25nm/20nm is achieved for metal gate nMOS/FUSI gate pMOS devices over the junction RTA reference. Optimal 0.26 fF/mum overlap capacitance values (at Vdd= | 1 | V), 18%/ 23% for nMOS/pMOS lower CV/I product and pMOS improved RSD are demonstrated

18% Efficiency IBC Cell With Rear-Surface Processed on Quartz

In order to relax the mechanical constraints of processing thin crystalline Si wafers into highly efficient solar cells, we propose a process sequence, where a significant part of the process is done on module level. The device structure is an interdigitated-back-contact cell with an amorphous silicon back surface field. The record cell reaches an independently confirmed efficiency of 18.4%. Although the device deserves further optimization, the result shows the compatibility of processing on glass with efficiencies exceeding 18%, which opens the door to a high-efficiency solar cell process where the potentially thin wafer is attached to a foreign carrier during the full processing sequence.

High-quality epitaxial foils, obtained by a layer transfer process, for integration in back-contacted solar cells processed on glass

Foil creation by lifting off a thin layer of a high quality silicon substrate is one of the promising substitutes for wafer sawing to create substrates thinner than 100 μm. The porous silicon-based layer transfer process is a well known method to obtain high quality foils. Despite a number of convincing lab-based solar cell show-cases, there is no breakthrough of this technology at (semi)-industrial level, because of the poor yield of processing free standing foils. This paper presents a method to fabricate back contacted solar cells based on epitaxial foils avoiding processes on free-standing foils. First, a porous silicon layer is electrochemically etched, acting as a weak sacrificial layer to detach the foil that is epitaxially grown on top of the porous silicon layer. Characterization of the epitaxial foils shows a good crystalline quality and an effective lifetime around 100 μs. Those results give indications that the obtained foils are well suited for solar cell fabrication. Front-side processing is done while the epitaxial foil is still attached to its parent substrate. A good yield is obtained for epitaxial foils that underwent the front-side processing sequence consisting of wet chemical texturing, FSF formation, passivation and ARC deposition. Afterwards, the front-side of the foil is bonded to a glass carrier and the foil is detached from its parent substrate. Silicone adhesives are used for this permanent bond. The rear-side of the solar cell is processed while bonded to glass. Therefore, only low temperature processes (<;200°C) can be used. So far, the rear-side processing sequence was performed on Float-zone reference wafers as a proof of concept resulting in a confirmed maximum efficiency of 18.4%. The rear-side processing sequence still needs to be applied on epitaxial foils.

Metal gate thickness optimization for MuGFET performance improvement

In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization of MuGFETs and the physical analysis of their gate stacks, we show that the thickness of the TiN metal gate affects the nature of its reaction with the gate dielectric. This, in return, results into threshold voltage (VT) and gate inversion thickness (Tinv) modifications which can explain performance enhancement in n-FETs without any performance loss in p-FETs.

Accurate Gate Impedance Determination on Ultraleaky MOSFETs by Fitting to a Three-Lumped-Parameter Model atFrequencies From DC to RF

We present an experimental methodology that demonstrates the suitability of the conventional three-lumped- parameter model for gate impedance of MOSFET devices at frequencies from dc to the gigahertz range, which permits accurate extraction of model parameters. The parasitic effects at a high frequency are minimized by using radio frequency techniques (i.e., short return paths and de-embedding structures), whereas a robust parameter extraction algorithm overcomes possible instrument inaccuracies. When combined, these allow simultaneous extraction of all three parameters (i.e., Cgate, RDT and Rseries) from the model. The technique is applied to conventional SiO2 -based MOSFET devices and to ultraleaky HfO2 devices with aggressively scaled gate dielectric thickness.