Vijay Degalahal

Soft error and energy consumption interactions: a data cache perspective

Energy-efficiency and reliability are two major design constraints influencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability considering the on-chip data caches. First, we investigate the impact of two commonly used architectural-level leakage reduction approaches on the data reliability. Our results indicate that the leakage optimization techniques can have very different reliability behavior as compared to an original cache with no leakage optimizations. Next, we investigate on providing data reliability in an energy-efficient fashion in the presence of soft-errors. In contrast to current commercial caches that treat and protect all data using the same error detection/correction mechanism, we present an adaptive error coding scheme that treats dirty and clean data cache blocks differently. Furthermore, we present an early-write-back scheme that enhances the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Experimental results show that proposed schemes, when used in conjunction, can reduce dynamic energy of error protection components in L1 data cache by 11% on average without impacting the performance or reliability.

Compiler-directed instruction cache leakage optimization

Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processors power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.

Methodology for high level estimation of FPGA power consumption

Power consumption in FPGA designs calls for power-aware design and power budgeting early in the design cycle. In this work, we leverage the FPGA architecture to present an efficient and accurate methodology for pre-silicon dynamic power estimation of FPGA-based designs. Our methodology uses device-level simulations to characterize a coarse-grained architectural model and incorporates architectural parameters to estimate the dominant wire capacitance. Such an approach not only reduces the need for tedious and time consuming silicon characterizations but ensures accurate pre-silicon power predictions. We apply the methodology to estimate the power consumption of a state-of-the-art Spartan-3™ FPGA family, evaluate the estimation results against silicon measurements, and present a detailed power breakdown of the FPGA. Our results find that the routing resources and the clock to consume the maximum power.

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

The two dominant architectural choices for implementing efficient communication fabrics for SoCs have been transaction-based buses and packet-based networks-on-chip (NoC). Both implementations have some inherent disadvantages - the former resulting from poor scalability and the transactional character of their operation, and the latter from inconsistent access times and deterioration of performance at high injection rates. In this paper, we propose a transaction-less, time-division-based bus architecture, which dynamically allocates timeslots on-the-fly - the dTDMA bus. This architecture addresses the contention issues of current bus architectures, while avoiding the multi-hop overhead of NoCs. It is compared to traditional bus architectures and NoCs and shown to outperform both for configurations with fewer than 10 PEs. In order to exploit the advantages of the dTDMA bus for smaller configurations, and the scalability of NoCs, we propose a new hybrid SoC interconnect combining the two, showing significant improvement in both latency and power consumption.

Soft errors issues in low-power caches

As technology scales, reducing leakage power and improving reliability of data stored in memory cells is both important and challenging. While lower threshold voltages increase leakage, lower supply voltages and smaller nodal capacitances reduce energy consumption but increase soft errors rates. In this work, we present a comprehensive study of soft error rates on low-power cache design. First, we study the effect of circuit level techniques, used to reduce the leakage energy consumption, on soft error rates. Our results using custom designs show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. We also validate the effects of voltage scaling on soft error rate by performing accelerated tests on off-the-shelf SRAM-based chips using a neutron beam source. Next, we study the impact of cache decay and drowsy cache, which are two commonly used architectural-level leakage reduction approaches, on the cache reliability. Our results indicate that the leakage optimization techniques change the reliability of cache memory. More importantly, we demonstrate that there is a tradeoff between optimizing for leakage power and improving the immunity to soft error. We also study the impact of error correcting codes on soft error rates. Based on this study, we propose an adaptive error correcting scheme to reduce the leakage energy consumption and improve reliability.

Analyzing soft errors in leakage optimized SRAM design

Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltages cause increased leakage, smaller supply voltages and node capacitances can be a problem for soft errors. This work compares the soft error rates of some recently proposed SRAM leakage optimization approaches. Our results using designs in 70 nm technology show that many of these approaches may increase the soft error rates as compared to a standard 6T SRAM. Further, we demonstrate that there is a tradeoff between optimizing the leakage power and improving the immunity to soft error.

Compiler-Directed Instruction Duplication for Soft Error Detection

We experiment with compiler-directed instruction duplication to detect soft errors in VLIW datapaths. In the proposed approach, the compiler determines the instruction schedule by balancing the permissible performance degradation with the required degree of duplication. Our experimental results show that our algorithms allow the designer to perform tradeoff analysis between performance and reliability.

Analysis of soft error rate in flip-flops and scannable latches

Soft errors can be induced through radiation sources, with particles of low energy occurring far more frequently than particles of high energy. Therefore, smaller CMOS device are more easily affected by lower energy particles. Thus, soft errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating various designs in 70 nm, 1 V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the gate capacitance, the other improves the overall robustness of the circuit by replicating the master stage of the master-slave flip-flops, which leads to reduced power and area overhead.

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

Compiler-assisted soft error detection under performance and energy constraints in embedded systems

Soft errors induced by terrestrial radiation are becoming a significant concern in architectures designed in newer technologies. If left undetected, these errors can result in catastrophic consequences or costly maintenance problems in different embedded applications. In this article, we focus on utilizing the compilers help in duplicating instructions for error detection in VLIW datapaths. The instruction duplication mechanism is further supported by a hardware enhancement for efficient result verification, which avoids the need of additional comparison instructions. In the proposed approach, the compiler determines the instruction schedule by balancing the permissible performance degradation and the energy constraint with the required degree of duplication. Our experimental results show that our algorithms allow the designer to perform trade-off analysis between performance, reliability, and energy consumption.