Vikas Kaushal

A Study of Geometry Effects on the Performance of Ballistic Deflection Transistor

We present the results of an experimental study of dimensional ratios dependencies on the performance of a ballistic deflection transistor (BDT) operating in a quasi-ballistic regime. Experimental transconductance change based on geometry variations is studied for smaller and larger devices with channel width of 300 and 500 nm, respectively. Transconductance variation for a series of drain biases is also observed for a specific geometry and dimension. By means of Monte Carlo modeling we report the effect of different geometry parameters on the transfer characteristics of BDTs. The strength of the gate control in the InGaAs channel is analyzed.

Exploring Digital Logic Design Using Ballistic Deflection Transistors Through Monte Carlo Simulations

We present exploratory studies of digital circuit design using the recently proposed ballistic deflection transistor (BDT) devices. We demonstrate a variety of possible logic functions through simple reconfiguration of two drain-connected BDTs. We further propose the creation of a three-BDT logic cell to yield differential versions of each logic function, improving overall flexibility of BDT circuit design. Each of the proposed gate configurations has been verified through extensive numerical calculations using an in-house Monte Carlo simulator. Simulation results show that the proposed gate arrangements are capable of achieving 400-GHz operating frequencies at room temperature. A compact fit-based analytical model to aid circuit design using BDTs is also introduced.

Effects of a High-k Dielectric on the Performance of III–V Ballistic Deflection Transistors

This letter presents a first successful integration of a high-k dielectric, i.e., Al2O3, with III-V semiconductors in ballistic deflection transistors (BDTs). The Al2O3 is deposited using atomic layer deposition, which allows the formation of uniform layers along the walls of etched trenches. The BDT transfer characteristic shows strong dependence on the dielectric permittivity of the material filling the etched trenches. When Al2O3 is deposited in the trenches, the transconductance of the BDT is enhanced and shifted to lower gate bias. Moreover, the ratio between output and leakage currents was also enhanced.

Current transport modeling and experimental study of THz room temperature ballistic deflection transistors

In this paper, two different theoretical models, Comsol Multiphysics™ (a Finite Element Analysis tool), and a field solver Atlas/Blaze from Silvaco, are compared qualitatively to study the effect of the deflector position, its size and electric field on the charge transport and its distribution along the channel, resulting in current outputs and leakages in ballistic deflection transistors (BDT). Silvaco simulations and experimental results were then used to study the lateral charge transport as a result of variation in electric field distribution, which controls the charge current along the channel in BDT. The electric field dependence of gain is also studied with experimental and theoretical results.

Study of leakage current mechanisms in ballistic deflection transistors

In this paper, the Ballistic Deflection Transistor (BDT) is reviewed for variations in performance of the device including leakage with respect to geometry modifications. Monte Carlo and Silvaco modeling tools are used to study current leakage mechanism in BDT. Low power selection criteria and theory behind position of deflector in the device are examined. Since ballistic conduction is not dissipative, power loss should be low. Leakage can be reduced by placing deflector at about 25% of its own length lower than the exact centre of the device. Current leakages that occurred during device operation are compared with each other and with the output current. It is observed that magnitude of leakage current is distinct at different ports of the device. For a specific set of parameters, leakage is comparable to the output which essentially motivates to choose optimum device architecture.

Ballistic deflection transistor: Geometry dependence and boolean operations

In this work, a room temperature study of ballistic deflection transistors (BDTs) is performed. By applying various processing steps such as hard mask deposition, e-beam lithography, reactive ion etching, etc., BDTs were fabricated, and the interplay between the geometry and their performance is analyzed. The importance of the top drain terminal is also examined. The application of the BDT for different logic configurations on the basis of its asymmetric biasing behavior is studied. Using this concept, even a single BDT can be used as a logic gate.

Sub-THz frequency analysis in nano-scale devices at room temperature

In this work, we have performed a Monte Carlo (MC) simulation to study the THz response of two types of nanometer devices at room temperature, so called three terminal Y-Branch Junction (YBJ) [1] and Ballistic Deflection Transistor (BDT) [2]. This sub-millimeter frequency range in the electromagnetic spectrum is attracting more and more interest due to its broad range of applications, from medical diagnostic to industrial quality control or security-screening tools. Our modeling tool consists of an ensemble MC simulator of the electron dynamics, self-consistently coupled with a 2D Poisson solver (with the finite differences approach) [3]. This tool is quite appropriate for time domain simulation of these ballistic devices at room temperature, as it has already been demonstrated in previous works that provides very good match to measured results [3]. Both types of semiconductor nanodevices, based on high mobility InGaAs channels, due to their small size have a very high surface/volume ratio, so that surface effects at the boundaries play a significant role in the device behavior. To include the depletion effect, a negative surface charge density, σ, is included in the simulator, with a value extracted from measurements.

A study of effects of deflector position variation on leakage currents in ballistic deflection transistors

In this paper, leakage mechanisms in ballistic deflection transistors (BDT) are studied using Finite Element Analysis (FEA) based on a simple conductive media model, a BDT simulator based on the semi-classical billiard model, and experimental measurements. In BDT, by simply tailoring the architecture, the electron transport can be, to a large extent, modified and controlled to reduce leakage. Since the triangular deflector plays a significant role in the operation of BDT, the models take into account its position variation along the Y-axis. Experimental results also discuss leakages with the deflector position (DP) variation. Structural modifications in the BDT help in analysing the device functionality, and understanding the relationship between right drain output current (IRD), left drain output current (ILD) and top drain leakage currents (ITD) with device geometry.

Performance optimization of room temperature Deflection Transistors through modified geometry

In this paper, the current status of the ballistic deflection transistor (BDT) project is described. The project focuses on a development of a new class of devices based on the steering of the electron flux and the ballistic deflection effect. The results of the latest experiments show significant current response improvement through optimized geometry modifications.

Realization of Logic Operations Through Optimized Ballistic Deflection Transistors

In this paper, the utilization of recently proposed ballistic deflection transistors (BDT) is investigated for the realization of the complete family of logic functions. BDT performance is optimized through its structural modification which is followed by the Monte Carlo simulations for 2- input logic gate functionalities at room temperature. BDT is a quasi-ballistic planar device based on InGaAs/InAlAs/InP heterolayer. The faster non-scattering transport obtained in the two dimensional electron gas (2DEG) layer facilitates smaller transit time and high performance needed for high speed circuitry.