David Wolpert

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

We present a self-contained adaptive system for detecting and bypassing permanent errors in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of spare wires without interrupting the data flow. To detect permanent errors at runtime, a novel in-line test (ILT) method using spare wires and a test pattern generator is proposed. In addition, an improved syndrome storing-based detection (SSD) method is presented and compared to the ILT method. Each detection method (ILT and SSD) is integrated individually into the noninterrupting adaptive system, and a case study is performed to compare them with Hamming and Bose-Chaudhuri-Hocquenghem (BCH) code implementations. In the presence of permanent errors, the probability of correct transmission in the proposed systems is improved by up to 140% over the standalone Hamming code. Furthermore, our methods achieve up to 38% area, 64% energy, and 61% latency improvements over the BCH implementation at comparable error performance.

Managing Temperature Effects in Nanoscale Adaptive Systems

This book discusses new techniques for detecting, controlling, and exploiting the impacts of temperature variations on nanoscale circuits and systems. A new sensor system is described that can determine the temperature dependence as well as the operating temperature to improve system reliability. A new method is presented to control a circuit’s temperature dependence by individually tuning pull-up and pull-down networks to their temperature-insensitive operating points. This method extends the range of supply voltages that can be made temperatureinsensitive, achieving insensitivity at nominal voltage for the first time.

Temperature Effects in Semiconductors

The changes in temperature described in the previous chapter affect the speed, power, and reliability of our systems. Throughout this book, we will examine all three of these metrics, though the majority of our discussion will be on how temperature affects the speed performance. In this chapter, we discuss the problem of temperature variation at the device and circuit level. In Sect. 2.1, we provide a background on the material dependences on temperature. In Sect. 2.2, the normal and reverse temperature dependence regimes are described. In Sect. 2.3, we explore how these dependences change with technology scaling and the introduction of new processing materials, such as high-κ dielectrics and metal gates.

A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits

The temperature dependence of MOSFET drain current varies with supply voltage. Two distinct voltage regions exist—a normal dependence (ND) region where an increase in temperature decreases drain current, and a reverse dependence (RD) region where an increase in temperature increases drain current. Knowledge of the temperature dependence is critical for avoiding overheating and wasted performance from excessive guardbands. In this paper, we present the first temperature dependence sensor to detect whether a system is operating in the ND or RD region. The dependence sensor occupies an area of 985 NAND2 equivalent gates. The sensor consumes 15.9 pJ per sample at a supply voltage of 1 V, with a 1°C resolution over the military-specified temperature range of -55°C to 125°C.

nand Gate Design for Ballistic Deflection Transistors

This paper presents a nand gate designed using ballistic deflection transistors (BDTs). Room temperature BDT measurements are captured in an empirical device model to simulate multi-BDT logic design. Measurements from a fabricated BDT nand gate validate the multidevice model and demonstrate the promise of BDTs for nanoscale circuit design.

Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty

This paper presents a new circuit technique to reduce temperature-induced delay uncertainty. Programmable temperature compensation devices (PTCDs) are used to tune logic gate pull-up and pull-down networks to their respective temperature-insensitive operating points, dramatically improving thermal resilience. Over a -55°C to 125°C temperature range, the proposed technique is shown to decrease temperature-induced delay uncertainty by up to 91% compared to other temperature resilient methods. We explore the limitations of using multi-VT and adaptive body biasing approaches to achieve temperature insensitivity; the proposed method achieves insensitive operation at larger supply voltages than prior methods, providing temperature insensitivity at nominal voltage for the first time. We explain how to integrate PTCDs into a variety of logic gates as well as larger structures such as a 1-bit mirror adder. Applying the proposed method to a clock tree is shown to reduce temperature-induced clock skew by up to 98%. Process variations degrade the temperature resilience; however, the proposed approach still improves temperature resilience by ~50% over prior methods when these variations are considered. Furthermore, we propose a process variation-compensation system to maintain our PTCD methods temperature resilience.

Exploring Digital Logic Design Using Ballistic Deflection Transistors Through Monte Carlo Simulations

We present exploratory studies of digital circuit design using the recently proposed ballistic deflection transistor (BDT) devices. We demonstrate a variety of possible logic functions through simple reconfiguration of two drain-connected BDTs. We further propose the creation of a three-BDT logic cell to yield differential versions of each logic function, improving overall flexibility of BDT circuit design. Each of the proposed gate configurations has been verified through extensive numerical calculations using an in-house Monte Carlo simulator. Simulation results show that the proposed gate arrangements are capable of achieving 400-GHz operating frequencies at room temperature. A compact fit-based analytical model to aid circuit design using BDTs is also introduced.

A Sensor System to Detect Positive and Negative Current-Temperature Dependences

We present a sensor system that determines if the circuit current-temperature (I - T) dependence is positive or negative. While prior temperature sensors can prevent overheating and temperature-induced timing failures in systems with negative I - T dependences, the proposed sensor system can prevent these issues in systems with negative or positive I - T dependences. This capability will become increasingly critical as technology scaling results in positive I - T dependences occurring at near-nominal operating voltages. The fabricated sensor system occupies <; 0.05 mm2, consuming 310 nJ per sample with 20- μs latency in 0.35-μm technology. A process variation compensation unit is presented for the calibration of the temperature sensor, which has a temperature nonlinearity of as low as 0.2%. Sensor functionality is verified over a temperature range of 5°C-80°C and a voltage range of 0.6-3.3 V. The system is shown to achieve this improved functionality while maintaining comparable area, energy, and accuracy with alternative temperature sensor designs.

Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design

This paper presents a new technique that takes advantage of the differing temperature dependences in low-voltage interconnect links and higher voltage transceivers. The link and transceiver are dynamically retimed as the system temperature changes. This delay borrowing enables the link to maintain a frequency requirement despite temperature-induced frequency variations in excess of 200%, and enables the link to operate at lower voltages than possible with a non-temperature aware link. In addition to improved tolerance of environmental variations, the proposed approach achieves energy savings of up to 40% in a commercial 65 nm technology, including the energy overhead of the temperature-aware system. Further, the delay borrowing system is shown to decrease temperature-induced delay variations by 85%.

Ballistic deflection transistors and the emerging nanoscale era

This paper presents a brief survey of the state of the art in nanoscale electronics, with special emphasis on room-temperature nanoscale ballistic deflection transistors (BDTs) and T-branch junctions (TBJs). Both devices are planar structures etched into a two-dimensional electron gas (2DEG). Extremely low capacitances (∼0.2 fF) in the 2DEG system and low switching voltages (∼0.15 V) predict THz performance and ultra-low power consumption, making BDTs and TBJs among the most promising and versatile of ballistic nanoelectronic devices. Obstacles in circuit and logic design using the BDT are presented along with potential solutions. I–V characteristics from a fabricated BDT and simulation results from a two-input BDT NAND gate are provided. Future plans to facilitate large-scale integration are discussed.