Vincent Knopik

A Fully Digital 65nm CMOS Transmitter for the 2.4-to-2.7GHz WiFi/WiMAX Bands using 5.4GHz ΔΣ RF DACs

This paper describes a fully digital CMOS transmitter that meets the IEEE 802.11 b/g and 802.16e standards in the 2.4-to-2.7 GHz band, while taking into account the coexistence requirements when used in 2G/3G mobile handsets. The baseband signal is upsampled first to a sampling rate FM around 160MHz, using FIR interpolators. I/Q and DC precompensation is then applied, to eliminate the image and LO components at the RF output. A first fine digital gain stage controls the signal level in a 0 to -12 dB range. The baseband signal is then upsampled to Fc/4, where Fc is the carrier frequency in the 2.4 to 2.7 GHz range. As the ratio between Fc/4 and FM is not necessarily integer, a fractional-N interpolator has to be used. The interpolating ratio has 17 bits of resolution, which allows carrier frequencies on a 25 kHz raster, to satisfy all possible WiFi and WiMAX channel allocations.

20 dBm CMOS class AB power amplifier design for low cost 2 GHz-2.45 GHz consumer applications in a 0.13 /spl mu/m technology

The paper presents a medium power amplifier (PA) design for 2.4 GHz applications in pure 0.13 /spl mu/m CMOS technology. The design has been done with reliability concern and presents high current layout considerations. It consists of evaluating the maximum current in the access lines and sizing the devices as well, without degrading the overall performance. The front end is composed of two stages using several transistors in cascade configuration. It can deliver at least 20 dBm at the maximum output power with a measured compression point better than 16 dBm. The chip has been integrated in 0.13 /spl mu/m 1.2 V and 2.5 V STMicroelectronics CMOS technology. The power stage consumes 220 mA under 2.5 V.

0.18/spl mu/m thin oxide CMOS transceiver front-end with integrated T/sub x//R/sub x/ commutator for low cost Bluetooth solutions

This paper presents the improvement of a first RF front end design for Bluetooth without using any antenna switch based on V. Knopik (2002). It consists of reducing the number of inductances, 3 instead of 7, and using thin oxide MOS instead of thick oxide ones without degrading the overall performance. The receiver is composed of a low-noise amplifier and a mixer. The former is suitable for zero IF, quasi zero IF or low IF topology for which NF is 21dB, 16dB and 14dB respectively. The transmitter is composed of an image rejection mixer and a power amplifier. It can deliver 5dBm at the compression point with an image rejection better than -40dBc. The chip has been integrated in 0.18/spl mu/m 1.8V STMicroelectronics RFCMOS technology. It consumes 27mA in TX mode and 5.2mA in RX mode.

A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (PSAT) of 19.9 dBm and a 1-dB compressed output power (P-1dB) of 17.2 dBm while achieving maximum power added efficiency (PAEmax) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm2. To the authors knowledge, this amplifier presents the highest figure of merit (FoM ITRS) among 60 GHz PAs using silicon technology.

Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver

This paper describes a WCDMA direct conversion receiver which has been integrated in a BiCMOS SiGe-carbon process featuring 0.25 /spl mu/m/f/sub T/=60 GHz bipolar transistors. This receiver includes an integrated RF-front-end with local oscillator quadrature generator, 5/sup th/ order Butterworth analog baseband lowpass filter (LPF) and variable gain amplifier (VGA), cut-off frequency calibrator, DAC for DC-offset calibration, serial bus interface and voltage and current reference generators. In the high/low gain modes, this device consumes 25 mA and 20 mA respectively with 2.7 V power supply. The die is wire bonded directly on the validation board. Within the receive band, the measurements show 51 dB of overall gain, NF=5 dB, IIP3= -9 dBm, ICP1 = -15dBm.

A 28GHz self-contained power amplifier for 5G applications in 28nm FD-SOI CMOS

This paper presents a 28 GHz CMOS balanced Power Amplifier (PA) with integrated quadrature hybrid couplers to achieve robust load insensitivity for 5G phased array applications. The proposed balanced PA achieves a saturated output power (Psat) of 18.7dBm and a maximum Power Added Efficiency (PAEmax) of 12.4% with 17.5dB gain. It consumes 154mW and occupies 0.66mm2 of die area. Each power cell is based on class-AB Segmented Biased Push-Pull (SBPP) topology to improve both the AM-AM and AM-PM conversion. The circuit is implemented in 28nm UTBB FD-SOI CMOS technology taking, advantage of the back gate for threshold voltage adjustment.

A 1.95GHz 28dBm fully integrated packaged power amplifier presenting a 3G FOM of 80 (PAE+ACLR) designed in H9SOIFEM CMOS 130nm: Development of an optimized high performances RF SOI power cell

A fully integrated and packaged Power Amplifier (PA) has been realized in 130nm STMicroelectronics H9SOIFEM. The PA is based on a new dedicated power cell delivering very good RF performances. At 28dBm output power, ACPR is -40dBc and PAE is 40%, reaching a FOM (ACPR+PAE) of 80 at 1.95GHz 3G standard, under 3.4V. Neither linearization nor efficiency enhancement technics have been used. The core power transistor provides very high power added efficiency (PAE) of 75% at a gain of 18dB typical, around 2GHz. This technology has been optimized for low cost RF front end module (FEM) applications.

Design of high performance CMOS power amplifiers for 60 GHz applications

Nowadays, wireless system data rates are limited to a few hundreds of Mbits/s due to the available spectrum limiting their bandwidth. However, due to a growing demand for very high data rate transmissions, as for example for HD video transfer or HDMI cable replacement, several standards have been proposed in the 60 GHz IMS band. With 9 GHz of available bandwidth, this frequency band is appropriate for short range multi-Gbit/s transmission. III–V technologies, such as GaAs or InP, are commonly used at such high frequencies as they provide higher performances than CMOS technologies. SiGe silicon technologies are also a good alternative to III–V technologies. However, all those technologies are too expensive with a manufacturing capacity and integration density much lower than CMOS technologies. There are therefore not competitive compared to CMOS for 60 GHz mass markets. To address 60 GHz emerging applications, most of millimeter wave transceiver parts have been recently integrated with success on the same substrate using CMOS process. Nevertheless, the integration of the power amplifier remains challenging as CMOS transistors have low gain and breakdown voltages. Furthermore a high quiescent power is inevitable to achieve high linearity required by the complex modulation scheme used to achieve high data rates.