Vincent O'Brien

A2DTest: A complete integrated solution for on-chip ADC self-test and analysis

An on-chip BIST solution performing accurate ADC measurements is presented. The platform enables linear and dynamic testing to occur in parallel, significantly lowering test time and cost. On-chip hardware resources are optimized for ADC test application.

An on-chip solution for static ADC test and measurement

This paper presents a solution for implementing low-cost ADC BIST into a System-on-Chip design. The solution is based on generating a programmable ramp as a test signal into the ADC and measuring the linear parameters using the histogram based test. An original approach for accurately measuring the Hits-per-Code as the ramp traverses the ADC transfer curve is presented. In particular, it is shown that code transitions or code flicker noise have an impact on the overall accuracy. This test procedure permits a ramp generator implementation and test engine design that is predominantly a digital solution. Results demonstrate lower silicon area overheads and lower test time capability.

A high performance band-pass DAC architecture and design targeting a low voltage silicon process

Direct Digital Synthesis (DDS) systems generate adjustable high resolution phase and frequency signals that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance band-pass DAC architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power DAC is portable to standard CMOS processes and achieves 110dB narrowband SFDR performance using sigma-delta (µΔ) modulation and multi-bit current steering techniques. A 3rd order digital µΔ modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.

Dithered multi-bit sigma-delta modulator based DPWM for DC-DC converters

Multi-bit sigma-delta based digital pulse width modulators (DPWM) are used in the control of DC-DC converters in order to achieve high resolution and therefore high output voltage accuracy at switching frequencies up to multiple MHz. The standard sigma-delta modulators which have mainly been used in these DPWMs to date generate idle tones in the applied duty cycle which result in large oscillations in the output voltage. A dithered sigma-delta modulator is instead implemented here which eliminates these oscillations in the output voltage by adding a random signal before the quantizer in the sigma-delta modulator. The power spectral density of the duty cycle produced by the dithered sigma-delta modulator based DPWM shows a reduction in the undesirable idle tones and this is also verified experimentally using a buck converter prototype.

A prototype platform for system-on-chip ADC test and measurement

An optimal solution for implementing ADC Built-In-Self-Test into a SOC design is presented. ADC linear and dynamic testing occurs in parallel which reduces test time. A signal generator produces a ramp for linear histogram measurements and a sine-wave signal for dynamic tests. This platform permits a BIST design that is predominantly a digital solution and enables accurate testing using low silicon area.

High order mismatch noise shaping for bandpass DACs

This paper presents a stable 4th order mismatch shaping technique using vector feedback dynamic element matching (DEM). When combined with a multi-bit sigma delta modulator, this DEM system allows high resolution band pass signals to be produced, using a low resolution unary weighted DAC.

An SOC platform for ADC test and measurement

An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.

A Reduced Hardware ISI and Mismatch Shaping DEM Decoder

This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.

Experimental validation of DAC with nested bus-splitting EFM4 DDSM

This paper presents measured results for a fourth order nested bus-splitting Error Feedback Modulator (EFM4) with dynamic element matching and a four-bit DAC. The nested bus-splitting EFM4 can run approximately 38% faster than a conventional EFM4 on a Xilinx Virtex 5, with negligible degradation in spectral performance.