Mark Halton

Digital control law using a novel load current estimator principle for improved transient response

A method for the early detection of load transients using a current estimator for VR applications is presented. This technique combined with a new charge-balanced digital control law can improve the dynamic response to fast load transients. The key advantage of this new approach is the early detection of load transients which is independent of ADC sampling, where most existing solutions incorporate relatively expensive, complex and energy consuming high-speed ADCs. The presented method significantly reduces the inherent delay associated with fixed sampling detection in the control loop. The load current estimation during transient is critical for improved transient performance and allows the possibility of using a charge-balanced control law. Unlike existing algorithms, the presented control law is capable of implementing non-zero load lines required for VRMs. A full description of this control law is detailed. The current estimator technique and the charge-balanced digital control law are critically assessed using Matlab/Simulink. The resulting transient behaviour gives a significant improvement over conventional control schemes.

Efficiency-Based Current Distribution Scheme for Scalable Digital Power Converters

The trend in next-generation switched-mode power supplies will lead to modular, scalable solutions, which deliver power efficiently over a wide range of operation. This paper details a new approach to introduce more advanced control features to improve system efficiency into these scalable solutions. While these methods have been incorporated into multiphase converters in the past, they all require the distribution of information among the individual converters. An advantage of the proposed method is that it does not require such communication signals between the individual power supplies and is, therefore, fully scalable and cost effective. A system comprising individual, smart converters is proposed, where each converter regulates its respective output power to a level with high efficiency. Converters not required for the delivered output power are shut down. The proposed approach is analyzed theoretically. Implementation details for a field-programmable gate array experimental prototype system are given. The system performance for a four-converter prototype system is analyzed and discussed. The efficiency obtained is compared with the efficiency of a multiphase system with phase-shedding operation and the efficiency of a system with independent power converters without phase-shedding support.

FPGA-Based Digital Pulse Width Modulator With Optimized Linearity

This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counter-based coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB.

Automated optimization of generalized model predictive control for DC-DC converters

Generalized predictive control (GPC) offers a method of designing digital compensators directly in the discrete-time domain. In this paper, an automatic design process based on the optimization of a few GPC parameters is presented. The application to DC-DC converters offers real benefits because of its clearly defined design process, time-domain performance criteria, simple tuning technique and guarantee of stability. For practical applications, the guarantee of stability may not be sufficient, certain performance criteria must also be achieved. In this design process, a performance index is used in the optimization routine to quantify specific performance objectives. A novel performance index is presented which weights performance and robustness for a more optimized compensator design. For illustration purposes an optimal GPC compensator is designed and tested for a buck converter. The resulting compensator is critically assessed in simulation and validated with experimental hardware.

Digitally controlled isolated SMPC with bidirectional data transmission scheme

This paper details the design of a digitally controlled isolated SMPC containing a novel bi-directional data transmission scheme The bi-directional data transmission scheme avoids the effects of opto-coupler aging, allows the use of digital control techniques and enables transmission of auxiliary data from primary-to -secondary and secondary-to primary. The complete digital controller was implemented on one custom and two FPGA boards.

FPGA-based multi-phase digital pulse width modulator with dual-edge modulation

This paper proposes a new FPGA-based architecture for a multi-phase digital pulse width modulator (MP-DPWM). A novel fine-leading/coarse-trailing edge modulation is applied to allow the sharing of a single fine resolution block for all phases. Specifically, the architecture takes advantage of Digital Clock Manager (DCM) blocks available in modern FPGAs to produce four clock phases from a single clock input to increase the resolution by two bit. An optimized counter/shift-register block is detailed which reduces the size and increases the maximum clock frequency of the architecture for certain numbers of phases. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA 9-bit resolution with a switching frequency of 1 MHz and 2–16 phases.

Automatic multi-phase digital pulse width modulator

Current demands on switched-mode power supplies to deliver higher output power with improved efficiency are leading to an increased use of multi-phase power converters. With an increasing number of phases, special multi-phase digital pulse width modulators (DPWMs) prove advantageous over the parallel use of conventional DPWMs. In this paper a “smart” multi-phase DPWM is presented which incorporates a duty cycle distribution algorithm. This algorithm is based on the fastest execution of the duty cycle input command with respect to the number of switching actions per phase and switching cycle. The system provides good dynamic current sharing during transients and enables the use of “faster” digital loop compensators. Intrinsic support of a variable number of active phases (phaseshedding operation) and improved scalability over conventional designs complete the feature set. The proposed system has been implemented on an FPGA system and tested with a four-phase buck converter.

Efficient Bi-Directional Digital Communication Scheme for Isolated Switch Mode Power Converters

An efficient high-speed bi-directional data transmission scheme for isolated AC-DC and DC-DC switched mode power converters is presented. The bi-directional scheme supports fast, efficient and reliable transmission of digitally encoded data across the isolation barrier and enables primary side control, allowing effective start-up and a simple interface to system controllers. Another key feature is that the bi-directional communication is independent of coupler gain and degradation and only the minimum number of couplers is required. The digital interface can also be used to transmit auxiliary signals between both sides. For test purposes, the scheme has been implemented on FPGAs and verified using a custom-built SMPC board.

State-dependent ADC scheme for digitally isolated SMPC

This paper proposes a state-dependent Analog-to-Digital Conversion (ADC) scheme for digitally isolated Switched Mode Power Converters (SMPCs). The SMPC voltage range is subdivided into three different regions corresponding to the three different states the SMPC can be in: steady state and the two transient states “undershoot” and “overshoot”. Each state uses a different, optimised ADC transfer function where the steady state region is sampled with higher resolution than the transient regions. This scheme reduces the number of bits to be transfered across the isolation barrier and therefore accommodates the use of data couplers with lower bandwidth or increased switching frequency.

Hierarchical synthesis system with hybrid DLO-MOGA optimization

Purpose – The purpose of this paper is to present a hierarchical circuit synthesis system with a hybrid deterministic local optimization – multi‐objective genetic algorithm (DLO‐MOGA) optimization scheme for system‐level synthesis.Design/methodology/approach – The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence.Findings – This approach reduces the total number of simulation iterations required for optimization. Reduction in run time enables use of full transistor‐level models for simulation of critical system‐level sub‐blocks. Consequently, for system‐level synthesis, simulation accuracy is maintained. The approach is demonstrated for the design of pipeline analog‐to‐digital converters on a 0.35 μm process.Originality/value – The use of a hybrid DLO‐MOGA optimization approach is a new approach to improve hierarch...