Vincent Pott

Detection of a single magnetic microbead using a miniaturized silicon Hall sensor

Using a highly sensitive silicon Hall sensor fabricated in a standard complementary metal-oxide-semiconductor (CMOS) technology, we detect a single magnetic microbead of 2.8 μm in diameter. The miniaturized sensor has an active area of 2.4×2.4 μm 2, a sensitivity of 175 V/AT and a resistance of 8.5 k. Two detection methods, both exploiting the superparamagnetic behavior of the bead, are experimentally tested and their performances are compared. This work opens the way to the fabrication of low cost microsystems for biochemical applications based on the use of dense arrays of silicon Hall sensors and CMOS electronics.

4-terminal relay technology for complementary logic

A 4-terminal (4T) relay technology is proposed for complementary logic circuit applications. The advantage of the 4T relay design is that it provides a means for electrically adjusting the switching voltage; as a result, a 4T relay can mimic the operation of either an n-channel or p-channel MOSFET. Fabricated 4T relays exhibit good on-state current (Ion ≫ 700µA for VDS = 1V) and zero off-state leakage current. Low-voltage switching (≪ 2V) and low switching delay (100ns) are demonstrated by appropriately biasing the body terminal. Endurance exceeds 109 on/off cycles without stiction or wear issues. Complementary operation is demonstrated in a functional relay inverter circuit.

Mechanical Computing Redux: Relays for Integrated Circuit Applications

Power density has grown to be the dominant challenge for continued complementary metal-oxide-semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applications. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical switches, with particular emphasis on electromechanical relays since they are among the most promising for IC applications. Relay reliability and process integration challenges are discussed. Demonstrations of functional relay logic circuits are then presented, and relay scaling for improved device density and performance is described. Finally, the energy efficiency benefit of a scaled relay technology versus a CMOS technology with comparable minimum dimensions is assessed.

Design and reliability of a micro-relay technology for zero-standby-power digital logic applications

Micro-electro-mechanical (MEM) relays recently have been proposed for ultra-low-power digital logic applications because their ideal switching behavior can potentially allow the supply voltage (V<inf>DD</inf>) to be scaled down further than for CMOS devices [1–3]. This paper describes design techniques to achieve reliable (high-endurance) MEM relay operation. Prototype relays fabricated using a CMOS-compatible process are demonstrated to operate with low surface adhesion force, adequately low on-state resistance (≪ 100kΩ) over a wide temperature range (20°C–200°C), and ≫10⁹ on/off switching cycles in N<inf>2</inf> ambient without stiction- or welding-induced failure. Measured characteristics are well predicted by both ANSYS simulations and an analytical model. Using the calibrated analytical model, scaled relay technology is projected to achieve ≫10× energy savings over comparably sized CMOS technology at throughputs up to ∼100MHz.

Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOS transistor and a suspended metal membrane in a unique metal-over-gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (<20 nm) is essential for a high C/sub on//C/sub off/ ratio (>100) and a low spring constant (<100 N/m) is needed for low voltage (<5 V) actuation. An adapted fabrication process is reported.

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications

Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency [1]. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate switching device with steeper sub-threshold slope—i.e., lower VDD/Ion for the same Ion/Ioff [2]. One promising class of such devices with nearly ideal Ion/Ioff characteristics are electro-statically actuated micro-electro-mechanical (MEM) switches [6]. Although mechanical movement makes MEM circuit delay significantly larger than that of CMOS, we have recently shown that with optimized circuit topologies MEM switches may potentially enable ∼10x lower energy over CMOS at up to ∼100MHz frequencies [3].

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation. The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts. A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa. A very high yield (>90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet. Device characteristics are reported from cryogenic temperature (T = 5 K) up to 150 degC, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated. Low field mobility for electrons up to 850 cm2 /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain. In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at T = 5 K. This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform.

Perfectly Complementary Relay Design for Digital Logic Applications

A dual-ended (¿seesaw¿) relay design is proposed for ultralow-power digital logic applications. Fabricated seesaw relays demonstrate a perfectly complementary switching behavior that is symmetric about V DD/2, with extremely steep switching behavior (< 0.1 mV/dec) and low on -state resistance (< 1 k¿). The perfectly complementary and symmetric operation provides for maximum operating voltage margin and minimal crowbar current, as evidenced by an abrupt inverter voltage transfer characteristic.

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive

A hybrid single electron transistor/MOSFET (SETMOS) circuit cell architecture, working as a three-terminal stand-alone device for obtaining SET-like Coulomb blockade oscillations, along with a high current drive ( /spl sim/ /spl mu/A), is proposed. SETMOS characteristics are successfully predicted by analytical models at subambient (-100 /spl deg/C to -150 /spl deg/C) temperature with realistic device parameters. The effect of bias voltages and current on the SETMOS Coulomb blockade oscillations characteristics is critically discussed. It is also demonstrated that the SETMOS can be converted into a unique quasi-periodic negative differential resistance (NDR) device by short-circuiting its gate and drain terminals.