Hei Kam

A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

Integrated circuit design with NEM relays

To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nano-electro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I/O that can significantly improve the energy efficiency of the whole VLSI system. By exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that NEM relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over CMOS adders with ns-range delays and with no area penalty. By applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. Similar improvements in high-speed I/O energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.

4-terminal relay technology for complementary logic

A 4-terminal (4T) relay technology is proposed for complementary logic circuit applications. The advantage of the 4T relay design is that it provides a means for electrically adjusting the switching voltage; as a result, a 4T relay can mimic the operation of either an n-channel or p-channel MOSFET. Fabricated 4T relays exhibit good on-state current (Ion ≫ 700µA for VDS = 1V) and zero off-state leakage current. Low-voltage switching (≪ 2V) and low switching delay (100ns) are demonstrated by appropriately biasing the body terminal. Endurance exceeds 109 on/off cycles without stiction or wear issues. Complementary operation is demonstrated in a functional relay inverter circuit.

Mechanical Computing Redux: Relays for Integrated Circuit Applications

Power density has grown to be the dominant challenge for continued complementary metal-oxide-semiconductor (CMOS) technology scaling. Together with recent improvements in microrelay design and process technology, this has led to renewed interest in mechanical computing for ultralow-power integrated circuit (IC) applications. This paper provides a brief history of mechanical computing followed by an overview of the various types of micromechanical switches, with particular emphasis on electromechanical relays since they are among the most promising for IC applications. Relay reliability and process integration challenges are discussed. Demonstrations of functional relay logic circuits are then presented, and relay scaling for improved device density and performance is described. Finally, the energy efficiency benefit of a scaled relay technology versus a CMOS technology with comparable minimum dimensions is assessed.

A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics

An accumulation-mode design for nanometer-scale electromechanical-gate field effect transistors (NEMFETs) is proposed and studied via simulation. In the off state, the gate electrode is in contact with the thin gate dielectric and short-channel effects are effectively suppressed. In the on state, the gate electrode is separated from the thin gate dielectric so that the threshold voltage VT is dynamically lowered and the transistor drive current I on is enhanced, and gate leakage is eliminated. The NEMFET can likely meet performance specifications for low-power applications at 25 nm gate length, and is attractive for scaled supply voltage operation

Design and reliability of a micro-relay technology for zero-standby-power digital logic applications

Micro-electro-mechanical (MEM) relays recently have been proposed for ultra-low-power digital logic applications because their ideal switching behavior can potentially allow the supply voltage (V<inf>DD</inf>) to be scaled down further than for CMOS devices [1–3]. This paper describes design techniques to achieve reliable (high-endurance) MEM relay operation. Prototype relays fabricated using a CMOS-compatible process are demonstrated to operate with low surface adhesion force, adequately low on-state resistance (≪ 100kΩ) over a wide temperature range (20°C–200°C), and ≫10⁹ on/off switching cycles in N<inf>2</inf> ambient without stiction- or welding-induced failure. Measured characteristics are well predicted by both ANSYS simulations and an analytical model. Using the calibrated analytical model, scaled relay technology is projected to achieve ≫10× energy savings over comparably sized CMOS technology at throughputs up to ∼100MHz.

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications

Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency [1]. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate switching device with steeper sub-threshold slope—i.e., lower VDD/Ion for the same Ion/Ioff [2]. One promising class of such devices with nearly ideal Ion/Ioff characteristics are electro-statically actuated micro-electro-mechanical (MEM) switches [6]. Although mechanical movement makes MEM circuit delay significantly larger than that of CMOS, we have recently shown that with optimized circuit topologies MEM switches may potentially enable ∼10x lower energy over CMOS at up to ∼100MHz frequencies [3].

Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages and large sensing margin. Because only dielectric and metal layers are required, this cell design is suitable for post-CMOS fabrication. As the cell area is reduced, low operating voltages can be maintained by scaling the vertical dimensions of the cell. Nanometer-scale electro-mechanical memory technology is therefore attractive for high-density embedded memory applications.

Perfectly Complementary Relay Design for Digital Logic Applications

A dual-ended (¿seesaw¿) relay design is proposed for ultralow-power digital logic applications. Fabricated seesaw relays demonstrate a perfectly complementary switching behavior that is symmetric about V DD/2, with extremely steep switching behavior (< 0.1 mV/dec) and low on -state resistance (< 1 k¿). The perfectly complementary and symmetric operation provides for maximum operating voltage margin and minimal crowbar current, as evidenced by an abrupt inverter voltage transfer characteristic.

Circuit-level requirements for MOSFET-replacement devices

Power consumption has grown to be the dominant challenge for continued CMOS scaling. This issue can be traced directly to the fact that the thermal voltage kBT/q does not scale, limiting the extent to which the MOSFET threshold voltage and hence the supply voltage (f/dd) can be scaled. To circumvent this limit, alternative switching device designs [1,2] which can achieve <60 mV/dec subthreshold swing (S) have been proposed and demonstrated. In this paper, we apply circuit-level metrics to establish guidelines for assessing the promise of alternative switching devices for replacing the MOSFET.