Vincent S. Chang

Achieving Conduction Band-Edge Effective Work Functions by

Conduction band-edge effective work functions (phi_m,eff) are demonstrated with TaC_x and TiN by means of La₂O₃ capping of HfSiO_x in a gate-first process flow with CMOS-compatible thermal budget. With TaC_x, a 10- Aring-thick La₂O₃ cap results in a phi _m,eff of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1-2 Aring) and unaffected electron mobility. With TiN, non-nitrided La₂O₃ capping results in a smaller phi_m,eff reduction at a larger EOT increase, while with post-cap nitridation, the TiN phi_m,eff is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on La₂O₃ capped stacks

\hbox{La}_{2}\hbox{O}_{3}

Cap layers have been used to modulate the effective work function (EWF) for high- /metal-gate CMOS devices. We have investigated the impact of stacking cap layers on the EWF. Stacked cap layers consisting of two sequential cap layers, including, Al₂O₃, Dy₂O₃, Sc₂O₃ and La₂O₃, were formed on HfSiON or SiON as host dielectrics. It is demonstrated that the EWF change due to the stacked cap layers corresponds to the sum of the EWF change from each single cap layer. Furthermore, no host dielectric dependence on the shifts is observed. This behavior is attributed to the complete intermixing of the stacked cap layers with the host dielectrics.

Capping of Hafnium Silicates

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

The Impact of Stacked Cap Layers on Effective Work Function With HfSiON and SiON Gate Dielectrics

This letter reports the engineering of effective work function (EWF) for tantalum carbide (TaC) metal gate on high-k gate dielectrics. The dependence of EWF on Si concentration in HfSiO as well as nitridation techniques is revealed. The EWF was extracted by both terraced oxide and terraced high-k techniques with the bulk and interface charges taken into account. The incorporation of Si in Hf-based dielectrics results in an increase of EWF, while the presence of N tends to decrease the EWF. Plasma nitridation is found to be more effective in lowering the EWF than a thermal nitridation. The phenomena can be explained by the modification of TaC/high-k interface dipole moment, which arises from the electronegativity difference for various interface bonds. Based on the above findings, we proposed a novel approach to reduce the EWF of TaC on HfSiON by using a thin HfO2 cap layer after optimizing the nitridation. The MOSFET results show that this technique is able to achieve a lower Vt without degrading the device performance

Strain enhanced low-V T CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

In this letter, we report that by using a thin dysprosium oxide (Dy2O3)cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (Vt) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy2O3 cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement.

Effective Work Function Engineering of

Performance and reliability of I/O FinFET device were co-optimized by fin surface smoothing and LDD Si interstitialization with the aim at the scalability. The fin surface smoothing process demonstrated Ion-Vt performance improvement by +6% / +3% for I/O N/PMOS, along with +8% speed gain in I/O ring oscillators. And core devices leveraged the merit, exhibiting +2% Ion-Ioff benefit with comparable electrostatics and variability. For I/O NMOS drain design, LDD Si interstitialization implantation achieved Isub reduction and 2.5× hot-carrier lifetime improvement, thanks to the well-engineered enhanced diffusion.

\hbox{Ta}_{x}\hbox{C}_{y}

For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of <;45mV/V and sub-threshold swing of <;65mV/decade and competitive drive current. Static noise margin of ~90mV for the high density SRAM operated down to 0.45V is achieved.

Metal Gate on Hf-Based Dielectrics

The static electricity of wet clean was characterized by contactless surface voltage measurement on silicon oxide dielectric in this study. The paper shows surface static charge at wafer center caused by a single wafer spin cleaning tool. Deionized water (DIW) rinse was verified as the critical step of inducing static charge. It was demonstrated by metal oxide semiconductor (MOS) capacitor that such serious dielectric static charge would degrade gate oxide integrity (GOI). With dissolved CO2 to lower DIW resistance, surface static charge at wafer center is reduced and degraded GOI is restored as a result.

Demonstration of Metal-Gated Low

Recently, thin rare-earth oxide dielectric capping layers between the high-k and metal gate have been used to modulate the threshold voltage (Vt) of MOSFETs [Kirsch et al., 2006]. In Dy2O3-capped high-k based devices, we observe an anomalous PBTI behavior where the Vt decreases during stress. Results suggest that there are two competing mechanisms - diffusion of preexisting positively-charged species and electron trapping. The charged species is likely located in the mixed high-k dielectric and associated with the interaction between the host dielectric, cap, and metal gate.