Tze-Liang Lee

Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation

The gate-oxide downscaling limit in thermal-enhanced remote plasma nitridation (RPN) process for forming ultrathin gate dielectric has been extensively investigated. In this work, the radical-induced re-oxidation effect has been observed as the base-oxide thickness less than 20 /spl Aring/. Nevertheless, for the base-oxide thickness thicker than 17 /spl Aring/, the RPN process still can effectively reduce the equivalent oxide thickness (EOT) and almost no transconductance degradation is observed. Further thinning of the base oxide will degrade the reduction of EOT and the transconductance with the RPN process, due to the penetration of nitrogen radicals into the active region. The physical and electrical properties of the ultrathin oxides (10 /spl sim/ 20 /spl Aring/) affected by this radical penetration have been studied extensively as well. Finally, the thinnest thickness has been estimated by compromising the feasible base-oxide thickness, the degradation of device performance, and the gate leakage criteria. Based on the forementioned criteria, we rind the 14 /spl Aring/ EOT to be the downscaling limit of the gate-oxide thickness.

2.0 μm electroluminescence from Si/Si0.2Ge0.8 type II heterojunctions

A metal-oxide-semiconductor tunneling diode is used to emit electroluminescence from a Si/Si0.2Ge0.8 heterojunction. Besides the 1.1u2002μm and 1.6u2002μm infrared emission from the band edges of Si and SiGe, respectively, 2u2002μm infrared emission is also observed due to the radiative recombination between the electrons in the Si conduction band and the holes in the SiGe valence band. This type II recombination can emit photons whose energy is below the SiGe band gap to extend the emission range of Si/Ge-based light-emitting devices. The emission line shape can be fitted by the electron-hole-plasma recombination model.

Superior n-MOSFET Performance by Optimal Stress Design

The high-performance n-FET is achieved by ultra- high-stress contact-etch-stop-layer stressor and optimal design of device dimensions. The biaxial-like stress resulting from a high symmetry in device dimension (gate width/gate length ratio is close to one) has the better performance in terms of Ion enhancement, ballistic efficiency, and injection velocity. The multichannel device with a smaller gate width/gate length ratio is proposed to enhance the device performance in the circuit design for the n-FET. The characteristics of the detailed stress simulation and the ballistic-transport measurement reported in this letter suggest that these results remain valid for ballistic-transport devices with 10-20-nm gate length. The stress distribution with different device dimensions was simulated by 3-D finite-element mechanical-stress simulation, and the mobility, ballistic efficiency, and injection velocity were calculated theoretically based on stress characteristics.

Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate

A low interface trap density (Dit) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance–voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interface trap density Dit close to 5.5 × 1011 cm−2 eV−1. The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future.

Gate width dependence on backscattering characteristics in the nanoscale strained complementary metal-oxide-semiconductor field-effect transistor

It is found that the ballistic efficiency, channel backscattering ratio, and injection velocity, which are the most important parameters for the ballistic transport, are greatly influenced by the stress characteristic in the channel even on the same gate length device. The narrower gate width device provides the best performance for the n-type field-effect transistor (n-FET) with the same gate length. Thus, the multichannel device is proposed to enhance the n-FET performance in the circuit design. The stress distribution with different device structures were simulated by the three-dimensional finite element mechanical stress simulation, and ballistic efficiency and injection velocity were calculated theoretically based on the stress characteristic. The theoretical calculation and the experimental data indicate the causes of the higher ballistic efficiency and injection velocity in narrower gate width devices to be the strain-induced modulation of the carrier mean-free path and smaller electron effective m...

Millisecond Anneal and Short-Channel Effect Control in Si CMOS Transistor Performance

In this letter, the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices are studied. The results reveal that the millisecond and spike annealing sequence plays an important role in the implanted boron p+/n junction formation. On blanket Si wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short-channel effect behaviors in the fabricated CMOS devices, resulting in opposite threshold-voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. The results also provide useful insights into ultrashallow-junction formation and short-channel effect control when scaling CMOS technology

High-Performance PMOS Devices on (110)/ Substrate/Channel with Multiple Stressors

A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% ION-IOFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111rang channel direction. The improvement is similar to that on conventional (100) substrate with lang110>rangchannel direction and can be explained by piezoresistive coefficients. Record PMOS device performance of Ion = 900 muA/mum at Ioff = 100 nA/mum and VDD = 1.0V for 40nm gate length is demonstrated

Digital communication using Ge metal-insulator-semiconductor light-emitting diodes and photodetectors

Both Ge light-emitting diodes and photodetectors are demonstrated by using the same metal-insulator-semiconductor (MIS) tunneling structure. A Ge MIS tunneling diode biased at the accumulation region is used as a light-emitting device and a Ge MIS tunneling diode biased at the inversion region is used as a photodetector. The ultrathin gate oxide film used in the MIS tunneling diode was grown by liquid phase deposition at 50u2009°C to lower the thermal budget. A Ge light-emitting diode has a higher quantum efficiency than a similar Si device (at least one order of magnitude stronger) due to the higher radiative recombination coefficient. With the detection of the Ge MIS photodetector, the data communication in free space is reported and demonstrated for the first time.

Improvement of short-channel characteristics of a 0.1-/spl mu/m PMOSFET with ultralow-temperature nitride spacer by using a novel oxide capped boron uphill treatment

In this work, the thermal annealing at 720/spl deg/C for 2 hr (called boron uphill treatment) with an SiO/sub 2/-capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-/spl mu/m PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough.

Characterization of plasma damage in plasma nitrided gate dielectrics for advanced CMOS dual gate oxide process

A comprehensive study on plasma induced degradation of gate oxide integrity (GOI) in remote plasma nitridation (RPN) process for advanced CMOS technology is presented. It is observed that device performance degradation caused by plasma nitridation will limit further reduction of gate leakage, albeit more than one order gate leakage current reduction can be achieved. NFETs, compared with pFETs, exhibit more Ig reduction while they also suffer more severely in Idsat degradation. Such phenomenon is ascribed to plasma induced damage since it is controversial to general characteristics of nitrided oxides. Evidence reveals that nitrogen radical indeed penetrates to Si/SiO/sub 2/ interface and causes radical-induced re-oxidation. Consequently, GOI of heavily nitrided oxides is degraded and such degradation is polarity dependent. Excessive electron trapping caused by plasma nitridation is believed to be responsible for the degradation. Therefore, plasma nitridation should be carefully treated for its further application in advanced CMOS technology.