Virgile Javerliac

High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits

Densely embedding Magnetic Tunnel Junctions (MTJ) in CMOS logic circuits is considered as one potentially powerful solution to bring non volatility, instant on/off and low standby power in todays programmable logic circuits, in order to overcome major drawbacks while preserving high operation speed. A critical issue in this process is the integration of MTJ electric signal to CMOS electronics, in particular the requirement of ldquozerordquo read/write error for logic applications. In this paper, we propose a new sense amplifier circuit, called Pre-Charge Sense Amplifier (PCSA). This circuit, comprising 7 CMOS transistors at minimum size, is able to read the magnetic configuration of a pair of magnetic tunnel junctions with opposite configurations at high speed (about 200 ps), with very low power and error rate compared to previously proposed solutions. Simulations using a ST Microelectronics 90 nm design kit and a compact model of MTJ demonstrate the performances of PCSA.

SPICE modelling of magnetic tunnel junctions written by spin-transfer torque

Spintronics aims at extending the possibility of conventional electronics by using not only the charge of the electron but also its spin. The resulting spintronic devices, combining the front-end complementary metal oxide semiconductor technology of electronics with a magnetic back-end technology, employ magnetic tunnel junctions (MTJs) as core elements. With the intent of simulating a circuit without fabricating it first, a reliable MTJ electrical model which is applicable to the standard SPICE (Simulation Program with Integrated Circuit Emphasis) simulator is required. Since such a model was lacking so far, we present a MTJ SPICE model whose magnetic state is written by using the spin-transfer torque effect. This model has been developed in the C language and validated on the Cadence Virtuoso Platform with a Spectre simulator. Its operation is similar to that of the standard BSIM (Berkeley Short-channel IGFET Model) SPICE model of the MOS transistor and fully compatible with the SPICE electrical simulator. The simulation results obtained using this model have been found in good accord with those theoretical macrospin calculations and results.

CMOS/Magnetic Hybrid Architectures

The general purpose of spin-electronics is to take advantage of the spin of the electrons in addition to their electrical charge to conceive innovative electronic components. These components combine magnetic materials which are used as spin-polarizer or analyzer together with semiconductors or insulators. SPINTEC Laboratory works on the development of these components and their integration in innovative hybrid CMOS/magnetic architectures. We study in particular the use of magnetic tunnel junctions (MTJ) for the design of magnetic random access memories (MRAM), magnetic FPGA (MFPGA) and non-reprogrammable logical devices (transceivers, adders, decoders). The design of these hybrid architectures requires to develop electrical equivalent models of the magnetic elementary components (magnetic tunnel junctions, spin-valves, Hall crosses) compatible with SPICE-like simulators. Complete simulations of the hybrid devices are performed before experimental realization and testing.

Dynamic compact model of thermally assisted switching magnetic tunnel junctions

The general purpose of spin electronics is to take advantage of the electron’s spin in addition to its electrical charge to build innovative electronic devices. These devices combine magnetic materials which are used as spin polarizer or analyzer together with semiconductors or insulators, resulting in innovative hybrid CMOS/magnetic (Complementary MOS) architectures. In particular, magnetic tunnel junctions (MTJs) can be used for the design of magnetic random access memories [S. Tehrani, Proc. IEEE 91, 703 (2003)], magnetic field programmable gate arrays [Y. Guillement, International Journal of Reconfigurable Computing, 2008], low-power application specific integrated circuits [S. Matsunaga, Appl. Phys. Express 1, 091301 (2008)], and rf oscillators. The thermally assisted switching (TAS) technology requires heating the MTJ before writing it by means of an external field. It reduces the overall power consumption, solves the data writing selectivity issues, and improves the thermal stability of the written...

Beyond MRAM, CMOS/MTJ Integration for Logic Components

Spintronics is a new discipline in which the spin of the electron is used as an additional degree of freedom besides its electrical charge to build innovative electronic components. Magnetic materials can be used as spin polarizer/analyzer in association with semiconductors or insulators, resulting in hybrid CMOS/magnetic architectures. Magnetic Tunnel Junctions (MTJ) are the basic elements of a new kind of memory, called MRAM (Magnetic Random Access Memory). Besides MRAM, it has recently been shown that by combining MTJ and CMOS components, one can also develop new functionalities for logic devices. This paper aims at giving a general overview of these novel hybrid magnetic/CMOS architectures and the design tools required for their design.

Towards an ultra-low power, high density and non-volatile Ternary CAM

Due to rapidly expanding networking industry demands, there is a corresponding need for high speed search capability, reduced power consumption and data masking within Content Addressable Memory (CAM) devices. These devices are used in applications requiring fast database searches. Image or voice systems, computer and communication systems are all CAM users. CAM have advantages in term of performance over other memory search algorithms. This is due to the simultaneous comparison of the desired information against the entire list of pre-stored entries. CAM have arrays designed to enable stored values to be located quickly by comparing input data to memory data to locate a match. This paper presents a design of a 18 Kb non-volatile Ternary Content Addressable Memory (TCAM) integrating Magnetic Random Access Memory (MRAM) devices. Magnetic Ternary Content Addressable Memory (MTCAM) can simplify conventional TCAM cell from sixteen transistors to 2 MRAM cells and 6 transistors. Furthermore, such device is intrinsically non volatile, e.g. power-failure-resistant. The MRAM cells are used both to store the information and to compare it (search) to the inputted data like an XOR logic function, whilst the CMOS part is used to detect and amplify the cell state.

Non-volatile register based on hybrid spintronics/CMOS technology

In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics 90 nm design kit and a complete MTJ Spice model for MRAM development, the delay propagation of this register is lower than 500 ps. We propose also the solutions to overcome the high sensitivity issue for this non-volatile register.