Guillaume Prenat

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I > Ico) and Neel-Brown model (I <; 0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication.

SPICE modelling of magnetic tunnel junctions written by spin-transfer torque

Spintronics aims at extending the possibility of conventional electronics by using not only the charge of the electron but also its spin. The resulting spintronic devices, combining the front-end complementary metal oxide semiconductor technology of electronics with a magnetic back-end technology, employ magnetic tunnel junctions (MTJs) as core elements. With the intent of simulating a circuit without fabricating it first, a reliable MTJ electrical model which is applicable to the standard SPICE (Simulation Program with Integrated Circuit Emphasis) simulator is required. Since such a model was lacking so far, we present a MTJ SPICE model whose magnetic state is written by using the spin-transfer torque effect. This model has been developed in the C language and validated on the Cadence Virtuoso Platform with a Spectre simulator. Its operation is similar to that of the standard BSIM (Berkeley Short-channel IGFET Model) SPICE model of the MOS transistor and fully compatible with the SPICE electrical simulator. The simulation results obtained using this model have been found in good accord with those theoretical macrospin calculations and results.

TAS-MRAM based Non-volatile FPGA logic circuit

As one of the most promising spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance and non-volatility. The integration of MRAM in FPGA allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, easily realize the dynamical reconfiguration and multi-context configuration. However, the conventional MRAM technology based on field induced magnetic switching (FIMS) writing approach consumes very high power and large circuit surface, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAMs further development in memory and logic circuit. Thermally assisted switching (TAS) based MRAM is then evaluated to address these issues and some design techniques for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90 nm technology, some chip characteristic results have been calculated to demonstrate the expected performance of TAS-MRAM based FPGA logic circuits.

CMOS/Magnetic Hybrid Architectures

The general purpose of spin-electronics is to take advantage of the spin of the electrons in addition to their electrical charge to conceive innovative electronic components. These components combine magnetic materials which are used as spin-polarizer or analyzer together with semiconductors or insulators. SPINTEC Laboratory works on the development of these components and their integration in innovative hybrid CMOS/magnetic architectures. We study in particular the use of magnetic tunnel junctions (MTJ) for the design of magnetic random access memories (MRAM), magnetic FPGA (MFPGA) and non-reprogrammable logical devices (transceivers, adders, decoders). The design of these hybrid architectures requires to develop electrical equivalent models of the magnetic elementary components (magnetic tunnel junctions, spin-valves, Hall crosses) compatible with SPICE-like simulators. Complete simulations of the hybrid devices are performed before experimental realization and testing.

Dynamic compact model of thermally assisted switching magnetic tunnel junctions

The general purpose of spin electronics is to take advantage of the electron’s spin in addition to its electrical charge to build innovative electronic devices. These devices combine magnetic materials which are used as spin polarizer or analyzer together with semiconductors or insulators, resulting in innovative hybrid CMOS/magnetic (Complementary MOS) architectures. In particular, magnetic tunnel junctions (MTJs) can be used for the design of magnetic random access memories [S. Tehrani, Proc. IEEE 91, 703 (2003)], magnetic field programmable gate arrays [Y. Guillement, International Journal of Reconfigurable Computing, 2008], low-power application specific integrated circuits [S. Matsunaga, Appl. Phys. Express 1, 091301 (2008)], and rf oscillators. The thermally assisted switching (TAS) technology requires heating the MTJ before writing it by means of an external field. It reduces the overall power consumption, solves the data writing selectivity issues, and improves the thermal stability of the written...

Spintronics-based Computing

This book provides a comprehensive introduction to spintronics-based computing for the next generation of ultra-low power/highly reliable logic. It will cover aspects from device to system-level, including magnetic memory cells, device modeling, hybrid circuit structure, design methodology, CAD tools, and technological integration methods. This book is accessible to a variety of readers and little or no background in magnetism and spin electronics are required to understand its content. The multidisciplinary team of expert authors from circuits, devices, computer architecture, CAD and system design reveal to readers the potential of spintronics nanodevices to reduce power consumption, improve reliability and enable new functionality.

Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications

A novel nonvolatile flip-flop based on spin-orbit torque magnetic tunnel junctions (SOT-MTJs) is proposed for fast and ultralow energy applications. A case study of this nonvolatile flip-flop is considered. In addition to the independence between writing and reading paths, which offers a high reliability, the low resistive writing path performs high-speed, and energy-efficient WRITE operation. We compare the SOT-MTJ performances metrics with the spin transfer torque (STT)-MTJ. Based on accurate compact models, simulation results show an improvement, which attains 20× in terms of WRITE energy per bit cell. At the same writing current and supply voltage, the SOT-MTJ achieves a writing frequency 4× higher than the STT-MTJ.

Spin-dependent phenomena and their implementation in spintronic devices

The general purpose of spinelectronis is to take advantage of the spin of electrons in addition to their charge to obtain new phenomena and conceive innovative electronic components. The first application of spinelectronics is in magnetoresistive heads for computer disk drives based on the giant magnetoresistance phenomenon. The discovery of tunnel magnetoresistance in magnetic tunnel junctions has allowed the emergence of a new kind of non-volatile memory called magnetic random access memory (MRAM). It potentially combines the advantages of all existing memories: non-volatility of FLASH, speed of SRAM, density of DRAM, hardness to ionizing radiations and endurance. Many research groups are nowadays investigating the use of these magnetic components for other logic applications. Spintronic phenomenon is the spin transfer effect allows controlling the magnetization of a magnetic nanostructure directly with a spin-polarized current. It attracts a considerable interest since it provides a new write scheme in MRAM and allows conceiving frequency tunable RF components.

Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing

This paper deals with a new MRAM technology whose writing scheme relies on the Spin Orbit Torque (SOT). Compared to Spin Transfer Torque (STT) MRAM, it offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths. These properties allow introducing SOT at all-levels of the memory hierarchy of systems and adressing applications which could not be easily implemented by STT-MRAM. We present this emerging technology and a full design framework, allowing to design and simulate hybrid CMOS/SOT complex circuits at any level of abstraction, from device to system. The results obtained are very promising and show that this technology leads to a reduced power consumption of circuits without notable penalty in terms of performance.

Beyond MRAM, CMOS/MTJ Integration for Logic Components

Spintronics is a new discipline in which the spin of the electron is used as an additional degree of freedom besides its electrical charge to build innovative electronic components. Magnetic materials can be used as spin polarizer/analyzer in association with semiconductors or insulators, resulting in hybrid CMOS/magnetic architectures. Magnetic Tunnel Junctions (MTJ) are the basic elements of a new kind of memory, called MRAM (Magnetic Random Access Memory). Besides MRAM, it has recently been shown that by combining MTJ and CMOS components, one can also develop new functionalities for logic devices. This paper aims at giving a general overview of these novel hybrid magnetic/CMOS architectures and the design tools required for their design.