Virginie Fresse

AVSynDEx: a rapid prototyping process dedicated to the implementation of digital image processing applications on multi-DSP and FPGA architectures

We present AVSynDEx (concatenation of AVS SynDEx), a rapid prototyping process aiming to the implementation of digital signal processing applications on mixed architectures (multi-DSP FPGA). This process is based on the use of widely available and efficient CAD tools established along the design process so that most of the implementation tasks become automatic. These tools and architectures are judiciously selected and integrated during the implementation process to help a signal processing specialist without relevant hardware experience. We have automated the translation between the different levels of the process to increase and secure it. One main advantage is that only a signal processing designer is needed, all the other specialized manual tasks being transparent in this prototyping methodology, hereby reducing the implementation time.

Rapid prototyping for mixed architectures

The aim of our work is to achieve a rapid prototyping dedicated to mixed architectures, made up of one multi-DSP part (software) and a FPGA architecture (dedicated hardware). We have determined a complete codesign methodology enabling to implement a complete digital signal or image processing line. The starting description associated with this methodology, is only a functional description, represented by a data flow graph. This global process developed for an automatic implementation enables the user to develop complex applications at a high level onto a complex architecture without any implementation pre-requirements.

An adaptive and predictive architecture for parameterised PIV algorithms

Particle image velocimetry (PIV) algorithms aim at flow visualisation and dynamic flow measurement. All existing PIV techniques are computing intensive and are mainly used in critical conditions. For a given experimental environment, several parameters must be set so that PIV algorithm must be parameterised. A dedicated architecture is therefore unsuitable unless it is adaptive. The aim of this work is to prove that our generic and adaptive FPGA-based system for real-time PIV applications previously designed can easily be modified when some parameters vary. From a unique structure and library of resources, the designer adapts the architecture according to the parameters. Time and resource prediction models help the designer to find the most suitable structure before the implementation process and ensure only one implementation without feedback. As a result, the design flow is fast and reliable

Evaluation of CPU and GPU architectures for spectral image analysis algorithms

Graphical Processing Units (GPU) architectures are massively used for resource-intensive computation. Initially dedicated to imaging, vision and graphics, these architectures serve nowadays a wide range of multi-purpose applications. The GPU structure, however, does not suit to all applications. This can lead to performance shortage. Among several applications, the aim of this work is to analyze GPU structures for image analysis applications in multispectral to ultraspectral imaging. Algorithms used for the experiments are multispectral and hyperspectral imaging dedicated to art authentication. Such algorithms use a high number of spatial and spectral data, along with both a high number of memory accesses and a need for high storage capacity. Timing performances are compared with CPU architecture and a global analysis is made according to the algorithms and GPU architecture. This paper shows that GPU architectures are suitable to complex image analysis algorithm in multispectral.

Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional Network on Chip (NoC) is not optimal for dataflow applications with large amount of data. On the opposite, point-to-point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data. For data communication inside the architecture, an efficient time-division multiplexed (TDM) architecture is proposed. This NoC uses a Fat Tree (FT) topology with Virtual Channels (VCs) and flit packet-switching with fixed routes. Two versions of the NoC are presented in this paper. The results of their implementations and their Design Space Exploration (DSE) on Altera Stratix II are analyzed and compared with a point-to-point communication and illustrated with a multispectral image application. Results show that a point-to-point communication scheme is not efficient for large amount of multispectral image data communications. An NoC architecture uses only 10% of the memory blocks required for a point-to-point architecture but seven times more logic elements. This resource allocation is more adapted to image analysis algorithms as memory elements are a critical point in embedded architectures. An FT NoC-based communication scheme for data transfers provides a more appropriate solution for resource allocation.

ARIAL: rapid prototyping for mixed and parallel platforms

The aim of this work is the achievement of a rapid prototyping process for the implementation of digital image processing applications on mixed and parallel architectures. The target platforms are made up of one multi-DSP part (software) and FPGA (dedicated hardware). This prototyping process includes the SynDEx tool as a low level tool to generate an optimized and distributed executive according to the platform. We propose to use as front-end tool a higher-level environment, Ptolemy, dedicated to the functional visualization and verification of signal or image-processing applications. An automatic translator is created to constitute the link between Ptolemy and SynDEx removing henceforth the manual translation stage. As a result, a signal-processing designer develops complex applications at a high level and can put the implementation on a complex architecture without any hardware pre-requirements. The prototyping process becomes fast and secured and the digital image-processing designer manages the whole development process and can easily achieve possible modifications. Currently ARIAL is a unique automatic prototyping process, which uses a functional description, for the implementation of applications on a multi-DSP + FPGA architecture.

Synthesis of dependency-aware traffic generators from NoC simulation traces

Networks-on-chip (NoCs) are currently the most appropriate communication infrastructure for many-core embedded systems. As NoCs become a de facto standard for on-chip systems, traffic generation models become critical for system-on-chip (SoC) design. Traditional trace-based traffic distorts the injection rate and the effects of congestion due to the lack of packets dependency information. They also have large data storage requirements. In this paper, we propose a new framework to process traces generated by message passing applications modeled as acyclic task graphs. This framework builds dependency-aware traffic generators (DATGs) by retrieving the packet dependencies from traces in a single simulation. The DATGs accurately replace the application nodes in emulations or simulations to explore the NoC design space. Our experimental analysis showed that our framework is more accurate than trace-based simulation for a broad range of NoC configurations. Moreover, our proposed framework uses only 3% of the data storage required by the traces.

Evaluation of NoC dedicated to multispectral image data communication

An efficient Network on Chip (NoC) is proposed for the data communication of multispectral image analysis algorithms on an adaptive architecture. A Butterfly Fat Tree (BFT) topology is used in this NoC on FPGA. Since there are large amount of data with different sizes in the NoC, Virtual Channels (VC) with flit packet-switching is chosen. Two versions of the NoC are presented in this paper. The results of the implementations on Altera StratixII and Xilinx Virtex4 are analyzed. It is shown that the required resources are similar but the frequency on Xilinx is much faster than on Altera.

System on chip FPGA designs of a parameterized particle image velocimetry algorithm

In this paper, an efficient architecture for particle image velocimetry algorithm is proposed. The aim of this work is the design of a system of chip FPGA that can be adapted to application characteristics (size of image, pixel clock frequency...). From these specifications, the designer defines the suitable number of processing modules. Required resources and execution time can also be predicted before the implementation process that makes the design flow faster and more secure

A survey of NoC evaluation platforms on FPGAs

Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on FPGAs, which improve the evaluation time and precision when compared to other solutions. There are different architectures of FPGA-based NoC evaluation tools. Details are scattered among several papers, making a comparative analysis hard to accomplish. This paper presents a comprehensive overview of FPGA tools for NoC evaluation. Our analysis covers aspects like network architecture, traffic generation and interface to the host PC. This provides insight on the platforms and their usefulness for different NoC evaluation tasks.