Todd C. Roggenbauer

Implementation of high-side, high-voltage RESURF LDMOS in a sub-half micron smart power technology

55 V high-side RESURF LDMOS has been integrated successfully in 0.35 /spl mu/m smart power technology by carefully arranging the lateral doping profile. This device has Rds.on/spl times/area of 0.55 m/spl Omega/.cm/sup 2/ with excellent safe operating area. With proper device terminal biasing scheme, this device can also be used as an isolated device. Techniques and issues related to the isolation is considered and discussed.

Stepped-Drift LDMOSFET: A Novel Drift Region Engineered Device for Advanced Smart Power Technologies

A novel drift region engineered stepped-drift LDMOSFET device in Freescales 0.25mum smart power technology is reported for the first time. The specific on-resistance of the device is 0.33 mOmegamiddotcm2 at breakdown voltage of 59 V, the best reported data to date. SOA of the device has been improved up to 87% compared to its conventional counterpart

Substrate Majority Carrier-Induced NLDMOSFET Failure and Its Prevention in Advanced Smart Power IC Technologies

This paper discusses substrate majority carrier conduction and prevention for an n-type lateral double diffused MOSFET (NLDMOSFET) device in Smart Power IC technologies. Substrate majority carrier current poses severe electrical and thermal stress for NLDMOSFET devices and causes many system integration issues for advanced Smart Power IC technologies. A single- and multi-iso isolated NLDMOSFET is proposed and experimentally verified to eliminate the problem. Tradeoff between device size, safe operating area (SOA), substrate current, and NLDMOSFET-device power dissipation has been studied. Detailed analysis of device SOA for conventional and isolated devices and techniques to improve the device SOA has also been provided

LDMOSFETs with Current Diverter for Smart Power Technologies

In this paper we propose and demonstrate a novel NLDMOSFET device concept, designed for deep sub-micron smart power technologies. The proposed device is designed with a P+ current diverter in the LDMOS drain so as to create a base-collector shorted PNP bipolar transistor from the source to the drain terminal of the LDMOS. Due to the inherent gain associated with the PNP device, the proposed LDMOSFET diverts more current in to the source/body terminal during reverse current injection phase, thereby reducing the amount of current that can get injected in to the substrate. Both single and double resurf LDMOSFETs have been investigated and dramatic improvement in substrate injection suppression is observed with no loss in breakdown voltage. Proposed devices also demonstrated significantly enhanced robustness and safe operating area (SOA)

Improved deep trench isolation breakdown voltage for SmartMOS

To achieve higher voltage analog and power devices, the deep trench isolation breakdown voltage must withstand the higher operating voltages. Optimization of deep trench etch to produce a straighter etch profile enable a void free poly filled trench, adding HF clean improve liner oxide film quality and changing liner oxidation process change the fill profile enable the oxide liner thickness to increase result in increase in the deep trench isolation (DTI) breakdown voltage.

Substrate Majority Carrier Induced NLDMOS Failure and Its Prevention in Advanced Smart Power Technologies

This paper discusses substrate majority carrier conduction and prevention for a NLDMOS device in smart power technologies. A multi-iso isolated NLDMOS is proposed and experimentally verified to eliminate the problem. Trade-off between device size, safe operating area, substrate current and NLDMOS device power dissipation has been studied

STI fill effect on poly-poly comb IL

Increasing ETD ratio for HDP oxide from 0.10 to 0.16 resulted in increasing film stress; film became more compressive. An increase in HF RF setting typically causes an increase in sputtering that may cause additional process induced damage or defects resulting in poorer oxide film quality, but the oxide wet etch rate ratio remain similar with increase in ETD which indicated no change in oxide quality. However, increasing etch to deposition ratio of HDP CVD film was demonstrated to improve gap fill of STI as indicated by a reduction in poly-poly comb shorts.

Optimization and Elimination of Parasitic Latchup in Advanced Smart Power Technologies

This paper examines CMOS latchup immunity for a wide range of structures in a 0.25 mum smart-power technology. The impact of logic ground isolation from the substrate and the presence p+ and n+ buried layers below the logic wells is quantified. Four different types of structures have been studied and it is demonstrated that certain ion-implantation layers that are inherently available in a standard deep submicron smart-power process due to medium and high-voltage requirements can be effectively utilized to optimize and improve the latchup performance of standard CMOS.