Vishnu Kamat

DPT restricted design rules for advanced logic applications

Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow. Only joint optimization in design rules between design, decomposition and process constraints can achieve the best scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware design tools are needed so that final designs can meet all DPT restricted design rules.

Enabling process window improvement at 45nm and 32nm with free-form DOE illumination

We present a method for optimizing a free-form illuminator implemented using a diffractive optical element (DOE). The method, which co-optimizes the source and mask taking entire images of circuit clips into account, improves the common process-window and 2-D image fidelity. We compare process-windows for optimized standard and free-form DOE illuminations for arrays and random placements of contact holes at the 45 nm and 32 nm nodes. Source-mask cooptimization leads to a better-performing source compared to source-only optimization. We quantify the effect of typical DOE manufacturing defects on lithography performance in terms of NILS and common process-window.

Accounting for mask topography effects in source-mask optimization for advanced nodes

We present a comprehensive study of applicability of a fast 3D mask model in the context of source-mask optimization to advanced nodes. We compare the results of source optimization (SO) and source-mask optimization (SMO) with and without incorporating a fast 3D mask model to the rigorous 3D mask simulations and wafer data at 22 nm technology node. We do this comparison in terms of process metrics such as depth of focus (DOF), exposure latitude (EL), and mask error enhancement factor (MEEF). We try to answer the question of how much the illumination shape changes with the introduction of mask topography effect. We also investigate if the illumination change introduces any mask complexity and at which level. Correlation between MEEF and any mask complexity due to source variation is also explored. We validate our simulation predictions with experimental data.

Calibration of e-beam and etch models using SEM images

Mask Process Compensation (MPC) corrects proximity effects arising from e-beam lithography and plasma etch processes that are used in the photomask manufacturing. Accurate compensation of the mask process requires accurate, predictive models of the manufacturing processes. Accuracy of the model in turn requires accurate calibration of the model. We present a calibration method that uses either SEM images of 2-dimensional patterns, or a combination of SEM images and 1D CD-SEM measurements. We describe how SEM images are processed to extract the contours, and how metrology and process variability and SEM alignment errors are handled. Extracted develop inspection (DI) and final inspection (FI) contours are used to calibrate e-beam and etch models. Advantages of the integrated 2D+1D model calibration are discussed in the context of contact and metal layers.

Free form source and mask optimization for negative tone resist development for 22nm node contact holes

In this paper we demonstrate the feasibility of Negative Tone Development (NTD) process to pattern 22nm node contact holes leveraging freeform source and model based assist features. We demonstrate this combined technology with detailed simulation and wafer results. Analysis also includes further improvement achievable using a freeform source compared to a conventional standard source while keeping the mask optimization approaches the same. Similar studies are performed using the Positive Tone Development (PTD) process to demonstrate the benefits of the NTD process.

Custom source and mask optimization for 20nm SRAM and logic

The 20nm generation for logic will be challenging for optical lithography, with a contacted gate pitch of ~82nm and a minimum metal pitch of ~64nm. A gridded design approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in logic designs.[1] The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. [2,3,4] A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip. However, modern SOCs include large amounts of SRAM memory as well. The proposed approach truly optimizes both, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches. We consider a design with the logic and SRAMs unified from the beginning. In this case, critical layer orientations as well as pitches are matched and each of the layers optimized for both functional sets of patterns. The layout for a typical standard cell using Gridded Design rules is shown in Figure 1a. The Gate electrodes are oriented in the vertical direction, with Active regions running horizontally. Figure 1b shows a group of SRAM bit cells designed to be compatible with the logic cell. The Gate orientation and pitch are the same. Optimization results will be presented for the co-optimization of critical layers for the cells. The Source-Mask Optimization (SMO) method used can optimize the illumination source [5] and mask for multiple patterns to improve the 2-D image fidelity and process window while controlling the mask sensitivity. It can incorporate the design intentions that are implied by Gridded Design rules. SMO will be done to balance complexity of the source and the complexity of the mask (OPC & MBSRAFs). A flexible approach to the optimization will be introduced.

PPC model build methodology: sequential litho and etch verification

We present a methodology for building through-process, physics-based litho and etch models which result in accurate and predictive models. The litho model parameters are inverted using resist SEM data collected on a set of test-structures for a set of exposure dose and defocus conditions. The litho model includes effects such as resist diffusion, chromatic aberration, defocus bias, lens aberrations, and flare. The etch model, which includes pattern density and particle collision effects, is calibrated independently of the litho model, using DI and FI SEM measurements. Before being used for mask optimization, the litho and etch models are signed-off using a set of verification structures. These verification structures, having highly two-dimensional geometries, are placed on the test-reticle in close vicinity to the calibration test-structures. Using through-process DI and FI measurement and images from verification structures, model prediction is compared to wafer results, and model performance both in terms of accuracy and predictability is thus evaluated.

Optimal segmentation of polygon edges

In optical proximity correction, edges of polygons are segmented, and segments are independently moved to meet line-width or edge placement goals. The purpose of segmenting edges is to increase the degrees of freedom in proximity correction. Segmentation is usually performed according to predetermined, geometrical rules. Heuristic, model-based segmentation algorithms have been presented in the literature. We show that there is an optimal and unique way of segmenting polygon edges.

RET for the wiring layer of a 3D memory

A typical wiring layer of SanDisk 3-dimensional memory device includes a dense array of lines. Every other line terminates in an enlarged contact pad at the edge of the array. The pitch of the pads is twice the pitch of the dense array. When process conditions are optimized for the dense array, the gap between the pads becomes a weak point. The gap has a smaller depth of focus. As defocus increases, the space between the pads diminishes and bridges. We present a method of significantly increasing the depth of focus of the pads at the end of the dense array. By placing sub-resolution cutouts in the pads, we equalize the dominant pitch of the pads and the dense array.