Huixiong Dai

Flexible Control of Block Copolymer Directed Self‐Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning

www.MaterialsViews.com C O M M U N IC A IO N He Yi , Xin-Yu Bao , Jie Zhang , Christopher Bencher , Li-Wen Chang , Xiangyu Chen , Richard Tiberio , James Conway , Huixiong Dai , Yongmei Chen , Subhasish Mitra , and H.-S. Philip Wong * Flexible Control of Block Copolymer Directed SelfAssembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning

22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)

Self-aligned double patterning (SADP) is a patterning technique that uses CVD spacers formed adjacent to a core (template) pattern that is defined by conventional lithography. After stripping the core (template) material, the spacers serve as a hardmask with double the line density of the original lithographically defined template. This integration scheme is an alternative to conventional double patterning for extending the half-pitch resolution beyond the current lithography tools half-pitch limit. Using a positive tone (spacer as mask) approach, we show capability to create 22nm line and space arrays, on 300mm wafers, with full wafer critical dimension uniformity (CDU) < 2nm (3 sigma) and line edge roughness (LER) < 2nm. These 22nm line and space results stem from template lithography using 1.2NA 193nm water immersion lithography. In this paper, we also demonstrate lot to lot manufacturability, the patterning of two substrate types (STI and silicon oxide trench), as well as demonstrate the formation of gridded design rule (GDR) building blocks for circuit design.

Gridded design rule scaling: taking the CPU toward the 16nm node

The Intel 45nm PenrynTM CPU was a landmark design, not only for its implementation of high-K metal gate materials1, but also for the adoption of a nearly gridded design rule (GDR) layout architecture for the poly silicon gate layer2. One key advantage of using gridded design rules is reduction of design rules and ease of 1- dimensional scaling compared to complex random 2-dimensinal layouts. In this paper, we demonstrate the scaling capability of GDR to 16nm and 22nm logic nodes. Copying the design of published images for the Intel 45nm PenrynTM poly-silicon layer2, we created a mask set designed to duplicate those patterns targeting a final pitch of 64nm and 52nm using Sidewall Spacer Double Patterning for the extreme pitch shrinking and performed exploratory work at final pitch of 44nm. Mask sets were made in both tones to enable demonstration of both damascene (dark field) patterning and poly-silicon gate layer (clear field) GDR layouts, although the results discussed focus primarily on poly-silicon gate layer scaling. The paper discusses the line-and-cut double patterning technique for generating GDR structures, the use of sidewall spacer double patterning for scaling parallel lines and the lithographic process window (CD and alignment) for applying cut masks. Through the demonstration, we highlight process margin issues and suggest corrective actions to be implemented in future demonstrations and more advanced studies. Overall, the process window is quite large and the technique has strong manufacturing possibilities.

Directed self-assembly defectivity assessment. Part II

The main concern for the commercialization of directed self-assembly (DSA) for semiconductor manufacturing continues to be the uncertainty in capability and control of defect density. Our research investigates the defect densities of various DSA process applications in the context of a 300mm wafer fab cleanroom environment; this paper expands substantially on the previously published DSA defectivity study by reporting a defect density process window relative to chemical epitaxial pre-pattern registration lines; as well as investigated DSA based contact hole shrinking and report critical dimension statistics for the phase separated polymers before and after etch, along with positional accuracy measurements and missing via defect density.

Decomposition strategies for self-aligned double patterning

Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques was previously limited by the lack of flexibility in terms of decomposition options , and significant developments were mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.

SRAM, NAND, DRAM contact hole patterning using block copolymer directed self-assembly guided by small topographical templates

Sublithographic patterning using Directed Self-Assembly (DSA) is demonstrated for practical circuits with non-periodic features. The DSA of irregularly distributed contact holes is guided by small topographical templates patterned by immersion 193 nm optical lithography. We experimentally demonstrate flexible and precise DSA control of 25 nm contact holes (centroid deviation∼1 nm) guided by 66 nm guiding templates for industry-standard 22-nm SRAM cells. Solution are also proposed to pattern contact holes (CD∼15 nm, Pitch∼40 nm, σ∼2 nm) for 15-nm NAND with two-hole templates and 2×-nm DRAM with three-hole templates. DSA is a low-cost, high-throughput extension of the double-patterning technique.

APF pitch-halving for 22nm logic cells using gridded design rules

The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF(R)-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela CanvaTM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.

Double patterning compliant logic design

Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before EUV or any other advanced patterning techniques become available. In general, there are two major double patterning techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadences Encounter Digital Implementation System (EDI System).

Mandrel-based patterning: density multiplication techniques for 15nm nodes

In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of using lithography as the principal process for generating device features, the role of lithography becomes to generate a mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to the scaling roadmap as the exposure tools themselves. Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash where layouts were simple and design space was focused. But today, the use of advanced automated decomposition tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails formed onto the substrate. In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of EUV+SADP.

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning

Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.