Hsu-Ting Huang

Full-chip OPC and verification with a fast mask 3D model

Mask topography (3D) scattering has to be taken into account for a more accurate solution of optical proximity correction (OPC) to meet the advanced Lithography patterning requirements. We report full-chip OPC and verification with a fast mask 3D model. To compare to the conventional mask model with Kirchhoff approximation, we performed lithography model calibration, OPC correction, and verification on a 40nm half-pitch BEOL metal layer using both approaches. OPC accuracies of both models are evaluated by measuring the critical dimension (CD) data on the printed wafer. OPC time with the fast 3D model is comparable to Kirchhoff model for the studied lithography configurations in this paper. Process windows of post-OPC layout are compared for both approaches.

Sequential PPC and process-window-aware mask layout synthesis

We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. The cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. This increases immunity to bridging in low contrast areas.

Accounting for mask topography effects in source-mask optimization for advanced nodes

We present a comprehensive study of applicability of a fast 3D mask model in the context of source-mask optimization to advanced nodes. We compare the results of source optimization (SO) and source-mask optimization (SMO) with and without incorporating a fast 3D mask model to the rigorous 3D mask simulations and wafer data at 22 nm technology node. We do this comparison in terms of process metrics such as depth of focus (DOF), exposure latitude (EL), and mask error enhancement factor (MEEF). We try to answer the question of how much the illumination shape changes with the introduction of mask topography effect. We also investigate if the illumination change introduces any mask complexity and at which level. Correlation between MEEF and any mask complexity due to source variation is also explored. We validate our simulation predictions with experimental data.

Free form source and mask optimization for negative tone resist development for 22nm node contact holes

In this paper we demonstrate the feasibility of Negative Tone Development (NTD) process to pattern 22nm node contact holes leveraging freeform source and model based assist features. We demonstrate this combined technology with detailed simulation and wafer results. Analysis also includes further improvement achievable using a freeform source compared to a conventional standard source while keeping the mask optimization approaches the same. Similar studies are performed using the Positive Tone Development (PTD) process to demonstrate the benefits of the NTD process.

PPC model build methodology: sequential litho and etch verification

We present a methodology for building through-process, physics-based litho and etch models which result in accurate and predictive models. The litho model parameters are inverted using resist SEM data collected on a set of test-structures for a set of exposure dose and defocus conditions. The litho model includes effects such as resist diffusion, chromatic aberration, defocus bias, lens aberrations, and flare. The etch model, which includes pattern density and particle collision effects, is calibrated independently of the litho model, using DI and FI SEM measurements. Before being used for mask optimization, the litho and etch models are signed-off using a set of verification structures. These verification structures, having highly two-dimensional geometries, are placed on the test-reticle in close vicinity to the calibration test-structures. Using through-process DI and FI measurement and images from verification structures, model prediction is compared to wafer results, and model performance both in terms of accuracy and predictability is thus evaluated.

Building a computational model for process and proximity compensation

Computational models used in process proximity correction require accurate description of lithography and etch processes. We present inversion of stepper and photoresist parameters from printed test structures. The technique is based on printing a set of test structures at different dose and defocus settings, and processing the CD-SEM measurements of the printed test structures. The model of image formation includes: an arbitrary pupil illumination profile, defocus bias, flare, chromatic aberrations, wavefront errors and apodization of the lens pupil; interaction of vector EM waves with the stack of materials on the wafer; and molecular diffusion in photoresist. The inversion is done by minimizing a norm of the differences between CDs calculated by the model and CD-SEM measurements. The corresponding non-linear least square problem is solved using Gauss-Newton and Levenberg-Marquardt algorithms. Differences between the CD measurements and the best fitting model have an RMS error of 1.63 nm. An etch model, separate from the lithography model, is fitted to measurements of etch skew.

Process and proximity correction, and verification for extreme ultraviolet lithography

Extreme ultra-violet (EUV) lithography has been planned for high-volume manufacturing (HVM) in 2014 for critical layers of advanced nodes in the semiconductor industry. Process and proximity correction (PPC) and verification is necessary in order to compensate various optical and other process effects in EUV lithography. Since the long-range flare, mask shadowing effect, and lens characteristics all vary throughout the whole mask range, position dependent PPC and verification may be needed for accurate mask pattern synthesis. In this paper, we will study the PPC accuracy. The PPC flow uses a single PPC kernel set and a full-mask flare map for long-range flare correction. The lithography model is calibrated in accordance with this PPC flow. The lithography model is used to perform full-mask correction for the 10nm node test chip mask for BEOL/FEOL short loop flow development. The optimized full-mask patterns were placed on the mask and printed using a 0.25 NA EUV scanner at various focus and dose conditions. Printed wafers were measured by a CD-SEM and compared to post-PPC verification results.

Model calibration and slit position effect on full-mask process and proximity correction for extreme ultraviolet lithography

Extreme ultra-violet (EUV) lithography is a promising solution for semiconductor manufacturing for the 1Xnm node and beyond. Due to the mask shadowing effect and strong flare, process and proximity correction (PPC) is required for EUV lithography even though the k1 factor is much larger than that in current 193nm immersion lithography. In this paper, we will report a procedure of model calibration and full-mask PPC flow for EUV lithography. To calibrate the EUV model, identical test structures are placed at various locations on the mask across the slit direction. Slit position effect, including mask shadowing effect, will be investigated at different locations. The wafer is patterned with a 0.25 NA EUV scanner and measured with CD-SEM for process evaluation and PPC model calibration. The EUV model is verified by wafer measurements. A PPC flow with mask shadowing effect compensation and model-based flare compensation is introduced to perform full-mask correction for the BEOL flow at 30nm HP L/S for the 16nm technology node. The slit position effect on PPC is investigated through post-PPC verification.

Optimal segmentation of polygon edges

In optical proximity correction, edges of polygons are segmented, and segments are independently moved to meet line-width or edge placement goals. The purpose of segmenting edges is to increase the degrees of freedom in proximity correction. Segmentation is usually performed according to predetermined, geometrical rules. Heuristic, model-based segmentation algorithms have been presented in the literature. We show that there is an optimal and unique way of segmenting polygon edges.

RET for the wiring layer of a 3D memory

A typical wiring layer of SanDisk 3-dimensional memory device includes a dense array of lines. Every other line terminates in an enlarged contact pad at the edge of the array. The pitch of the pads is twice the pitch of the dense array. When process conditions are optimized for the dense array, the gap between the pads becomes a weak point. The gap has a smaller depth of focus. As defocus increases, the space between the pads diminishes and bridges. We present a method of significantly increasing the depth of focus of the pads at the end of the dense array. By placing sub-resolution cutouts in the pads, we equalize the dominant pitch of the pads and the dense array.