Vladimir A. Ukraintsev

SCANNING CAPACITANCE SPECTROSCOPY : AN ANALYTICAL TECHNIQUE FOR PN-JUNCTION DELINEATION IN SI DEVICES

Scanning capacitance spectroscopy (SCS), a variant of scanning capacitance microscopy (SCM), is presented. By cycling the applied dc bias voltage between the tip and sample on successive scan lines, several points of the high-frequency capacitance–voltage characteristic C(V) of the metal–oxide–semiconductor capacitor formed by the tip and oxidized Si surface are sampled throughout an entire image. By numerically integrating dC/dV, spatially resolved C(V) curves are obtained. Physical interpretation of the C(V) curves is simpler than for a dC/dV image as in a single-voltage SCM image, so that the pn junction may be unambiguously localized inside a narrow and well-defined region. We show SCS data of a transistor in which the pn junction is delineated with a spatial resolution of ±30 nm. This observation is consistent with the conclusion that SCS can delineate the pn junction to a precision comparable to the Si depletion width, in other words, the actual size of the electrical pn junction. A physical model t...

pn-junction delineation in Si devices using scanning capacitance spectroscopy

The scanning capacitance microscope (SCM) is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope (SPM). As reported in Edwards et al. [Appl. Phys. Lett. 72, 698 (1998)], scanning capacitance spectroscopy (SCS) is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sam...

A comprehensive test of optical scatterometry readiness for 65-nm technology production

Measurement bias is a central concept of critical dimension (CD) metrology. Bias is a complex function of sample, tool and time. Bias variation defines the total measurement uncertainty (TMU). TMU is a measure of metrology quality. Precision (or bias variation with time) is only a part of TMU. Often tool-to-tool and sample-to-sample components of bias variation exceed precision. To measure sample-to-sample bias variation, knowledge of the reference CD value for the samples is required. Since bias is sample specific, the technology representative set of calibrated samples has to be created. The described approach has been implemented for a comprehensive evaluation of optical scatterometry (OS) to determine readiness of OS for the 65 nm technology production. The tests covered nine OS applications representative of the technology. The testing revealed that OS metrology is mostly ready to support 65 nm technology production. Both spectral ellipsometry and angular reflectometry OS compete closely on all applications. OS demonstrates acceptable averaged bias for CD and sidewall angle for most applications. Correlation of OS to other metrologies is usually satisfactory. At the same time some problems have been observed. The majority of the tested applications show poor linearity for some measured parameters. Cross-correlation between parameters is usually the cause. OS has trouble to meet the semiconductor industrys tight fleet precision requirements. For all applications, OS tool matching is a major component of fleet precision. The evaluation also exposed some general CD metrology challenges. With accuracy allowance in a sub-nanometer range, it is difficult to find an adequate reference technique to verify and calibrate OS models. Atomic force microscopy (AFM) has been chosen as a reference technique during this evaluation, but it has limitations. Precision, sidewall profile resolution and tip finite dimensions are some of the AFM limitations. OS fleet TMU for many applications is unacceptably high. Further work is needed to better understand the impact of reference data uncertainty on these alarming results. It is clear that to achieve a desired sub-nanometer agreement between reference and OS data, one must pay scrupulous attention to every detail of the experiment.

The role of AFM in semiconductor technology development: the 65 nm technology node and beyond

The International Technology Roadmap for Semiconductors (ITRS) predicts that atomic force microscopy (AFM) will become an in-line metrology tool starting at the 65 nm technology node. Others argue that AFM is not suitable beyond the 65 nm node due to probe size limitations. This presentation examines the current state of AFM in semiconductor technology development and manufacturing. The following AFM applications are reviewed: post chemical mechanical polishing (post-CMP) and post reactive ion etching (post-RIE) topography measurements, critical dimension (CD) scanning electron microscopy (SEM) and optical scatterometry (OCD) calibration and long-term accuracy monitoring, across integrated circuit (IC) CD bias measurements (OCD lines vs. real circuit), optical proximity correction (OPC) modeling verification, non-destructive 3D metrology (resist, gate, sidewall offsets, holes and trenches). This current state is contrasted with upcoming requirements, benefits and limitations of metrology tools. The topics include the following: an application specific analysis of AFM limitations, the merits and limitations of transmission electron microscopy (TEM) as reference technique for AFM, CD SEM and OCD, the impact of sample-to-sample bias variation on total measurement uncertainty of TEM, CD SEM, OCD and AFM, the unique role of AFM in establishing across CD metrology correlation and accuracy, and need for a new type of intelligent in-line CD metrology tools, which would combine the merits of OCD, CD SEM and AFM.

Review of reference metrology for nanotechnology: significance, challenges, and solutions

Metrology and control of critical dimensions (CDs) are key to the success of nanotechnology. Modern nanotechnology and nanometrology are largely based on knowledge developed during the last 10 to 20 years of semiconductor manufacturing. Semiconductor CD metrology entered the nanotechnology age in the late 1990s. Work on 130-nm- and 90-nm-node technologies led to the conclusion that precision alone is an insufficient metric for the quality assessment of metrology. Other components of measurement uncertainty (MU) must also be considered: 1. sample-to-sample measurement bias variation, 2. sampling uncertainty, and 3. sample variation induced by the probe-sample interaction. The first one (sample-dependent systematic error) is common for indirect and model-based CD metrologies such as top-down and cross-sectional scanning electron microscopy (SEM) and scatterometry (OCD). Unless special measures are taken, bias variation of CDSEM and OCD could exceed several nanometers. Variation of bias and therefore MU can be assessed only if reference metrology (RM) is employed. The choice of RM tools is very limited. The CD atomic force microscope (AFM) is one of a few available RM tools. The CDAFM provides subnanometer MU for a number of nanometrology applications. Significant challenges of CDAFM remain, such as the following: 1. the finite dimensions of the probe are limiting characterization of narrow high-aspect spaces, 2. the flexibility of the probe complicates positioning control, 3. the probe apex sharpness limits 3D AFM resolution, 4. the lifetime of atomically sharp probes is too short, and 5. adsorbates change properties and dimensions of nanometer-sized objects considerably. We believe that solutions for the problems exist; therefore, we will discuss the role of RM in nanometrology, current RM choices, and the challenges of CDAFM as well as suggest some potential solutions.

Spectral scatterometry for 2D trench metrology of low-K dual-damascene interconnect

A systematic study has been conducted to evaluate accuracy and precision of spectral scatterometry used for two-dimensional (2D) characterization of trenches formed in fluorinated silicon glass (FSG). Experiments were done on short-flow dual-damascene Cu interconnect material. Trench critical dimensions (CD) obtained using KLA-Tencors spectral scatterometer were correlated with data collected using CD atomic force microscope (AFM), CD scanning electron microscope (SEM) and transmission electron microscope (TEM). 3 major trench characteristics were analyzed: trench width, trench depth and sidewall angle. Spectral scatterometry demonstrated an excellent correlation (above 0.96) with CD AFM and SEM in tested trench width range of (80-240) nm and trench depth range of (410-450) nm. Spectral scatterometry showed acceptable correlation of 0.55 and minimal offset of 0.05 degrees with AFM in tested sidewall angle range of (87.5-89) degrees. Spectral scatterometry has demonstrated better than 1.0 nm and 0.2 degrees dynamic precision (3s) for both width and height and sidewall angle, respectively. We conclude that KLA-Tencors SpectraCD system is capable of accurate and precise 2D characterization of FSG trenches. We recommend scatterometry as a high throughput and non-destructive metrology for trench linewidth and depth monitoring in low-K dielectric interconnect manufacturing.

Silicon surface preparation for two-dimensional dopant characterization

Most two-dimensional (2D) dopant characterization techniques deal with near surface carrier concentration or surface potential measurements using a device cross-section. Thus, a reproducible and well-characterized surface condition is essential for accurate measurements. We report on an X-ray photoelectron spectroscopy study of surface preparation techniques commonly used in 2D dopant characterization: (i) hydrogen termination, (ii) colloidal silica polishing, (iii) low temperature silicon oxidation. Although the presented results may be applied to any other technique, in this report we concentrate on scanning capacitance microscopy (SCM). For high quality SCM a thin, uniform, and charge-free insulating film has to be formed on top of the silicon sample. Two phenomena may have a critical impact on accuracy of SCM: (i) leakage through the insulating layer and (ii) surface charging which may cause unpredictable variations in flat-band voltage. We found that samples polished by colloidal silica have about on...

Strong effect of dopant concentration gradient on etching rate

Dopant concentration sensitive etching of silicon in HF:HNO3:CH3COOH solution was studied using epitaxially grown silicon samples. The study has shown the unstable character of the process, significant time and structure size dependencies of the etching rate, as well as the dependence of the rate on the dopant concentration gradient. The data may be rationalized on the basis of the electrochemical and autocatalytic nature of the reaction. The influence of the dopant gradient and overall device geometry on the etching rate may cause significant inaccuracy of the dopant distribution measurements.

Transition from precise to accurate critical dimension metrology

A new measurement system analysis (MSA) methodology has been developed at Texas Instruments (TI) to evaluate the status of the 65 nm technology critical dimension (CD) metrology and its readiness for production. Elements of the methodology were used in a previously reported scatterometry evaluation [1]. At every critical process level the precision, bias, linearity and total measurement uncertainty (TMU) were evaluated for metrology fleet over extended periods of time, and with the technology representative set of samples. The samples with variations that fully covered and often exceeded process space were pre-calibrated by CD atomic force microscope (AFM). CD AFM measurement precision was determined for every analyzed process level based on repeated measurements conducted over several days. The National Institute of Standards and Technologies (NIST) traceable standards were used to verify CD AFM line CD and scale calibrations. Therefore, for the first time the NIST traceability has been established for CD metrology at every critical process level for the entire technology. The data indicates an overall healthy status of the 65 nm CD metrology. Sub-nanometer accuracy has been established for gate CD metrology. The thorough CD metrology characterization and specifically absolute CD calibration were instrumental in seamless technology transfer from 200 mm to 300 mm fabs. The qualification of CD metrology also revealed several problems. Most of these are well-known from previous studies and should soon be addressed. CD scanning electron microscopy (SEM) has a systematic problem with bias of CD measurements. The problem is common for several front-end and back-end of line process levels. For most process levels, TMU of CD SEM is noticeably affected by sample modification inflicted by electron irradiation (shrinkage, charging, buildups, etc.). This causes problems, especially in the case of fleet TMU evaluation. An improved data collection methodology should be devised to minimize the impact of sample modification on fleet TMU measurements. The reported progress in semiconductor industrial CD metrology became possible after a recent breakthrough in line CD standard technology [2,3], recognition of CD AFM as an instrument for CD traceability [4,5] and development of the concept and mathematical tools for TMU analysis [6,7].

Control of Polysilicon Surface Topography in a High Selectivity Chemical Mechanical Polishing Process

Characterization of a high selectivity polysilicon chemical mechanical polishing (CMP) is studied in this report. The process is developed for the fabrication of two-dimensional secondary ion mass spectrometry (2D SIMS) test chip, in which a silicon trench is filled with polysilicon and polished back in an effort to create a flat surface. In this application, the polysilicon surface roughness and the step height between polysilicon and c-Si substrate must be minimized. Atomic force microscopy shows that the CMP process reduces polysilicon surface roughness. The step height between polysilicon and c-Si substrate can be minimized by choosing the proper thickness for the polish-stop layer (e.g., silicon nitride) over the c-Si surface. We found that the step height between the polysilicon and the c-Si surface is relatively sensitive to the opening of the trench, but not sensitive to slurry selectivity and total polishing time. We speculate that deformation of the polishing pad is critical for the trench recess. In addition, we discuss important issues of characterizing the trench recess. Using a histogram of height, the high and low modes of the distribution are sometimes used to identify the trench recess. We showed that this approach results in various offsets from the peak-to-valley height.