Vobulapuram Ramesh Kumar

An Accurate FDTD Model for Crosstalk Analysis of CMOS-Gate-Driven Coupled RLC Interconnects

This paper accurately models the crosstalk effects in a CMOS-gate-driven coupled RLC interconnects using the nth power law model and finite-difference time-domain (FDTD) technique. The propagation delay, peak crosstalk voltage, and peak voltage timing on victim line of coupled-multiple lines are observed and compared to HSPICE simulation results for the global interconnect length at 32 nm technology node. The numerical results illustrate that the proposed model accurately estimates the performance parameters of driver interconnect load system. An average error of less than 2% is observed in estimation of peak crosstalk voltage and its timing. The proposed model can be extended for coupled n lines and useful for the evaluation of signal integrity, issues of EMI, and EMC of on-chip interconnects.

An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

Abstract An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.

Time and Frequency Domain Analysis of MLGNR Interconnects

Multilayer graphene nanoribbons (MLGNRs) have potentially provided attractive solutions in an intensely growing researched area of interconnects. However, for MLGNR interconnects, the doping is inevitable since the conductivity of neutral MLGNR is much lower than even Cu. Therefore, a doped MLGNR can potentially exhibits smaller resistance in comparison to Cu wires. This paper analyzes and compares the power, delay, and bandwidth performance of Cu and doped MLGNR using an equivalent single conductor model. For similar dimensions, the overall delay and power dissipation of doped MLGNR is substantially smaller by 86.13% and 43.72%, respectively, in comparison to the Cu interconnects. Moreover, MLGNR demonstrates prominently improved bandwidth and relative stability at global interconnect dimensions. However, a narrow width MLGNR in a realistic scenario exhibits rough edges that significantly reduces the mean free path and, thereby, raises its resistance. Considering these facts, this paper for the first time analyzes and compares the performance of Cu and MLGNR interconnects with different edge roughness conditions.

An Unconditionally Stable FDTD Model for Crosstalk Analysis of VLSI Interconnects

In this paper, an unconditionally stable finite-difference time-domain (US-FDTD) model is proposed for the crosstalk noise analysis of coupled very large scale integration interconnects. The accuracy of the proposed model is validated against the conventional FDTD model and HSPICE. It is observed that the proposed model is as accurate as the conventional FDTD and HSPICE. It is also observed that the stability of the proposed model is not constrained by the Courant-Friedrichs-Lewy stability condition. Depending on the time-step size, the proposed model can be up to 100× faster than the conventional FDTD.

Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique

Abstract This paper presents an accurate and efficient model for the transient analysis of multiwall carbon nanotubes (MWCNT) using finite-difference time-domain (FDTD) method. The proposed model can be essentially used to analyze the functional and dynamic crosstalk effects of coupled-two MWCNT interconnect lines. Using the proposed model the voltage and current can be accurately estimated at any point on the interconnect line and furthermore, the model can be extended to coupled-n interconnect lines with a low computational cost. Crosstalk induced propagation delay, peak voltage, and its timing instance are measured using the proposed model and validated by comparing it to the HSPICE simulations. Over a random number of test cases it is observed that the average error in estimating the noise peak voltage on a victim line is less than 1%. The proposed model is extremely useful for accurate estimation of crosstalk induced performance parameters of MWCNT interconnects.

Graphene Based On-Chip Interconnects and TSVs : Prospects and Challenges

In the first four decades of the semiconductor industry, the system performance was entirely dependent on transistor delay and power dissipation. With technology scaling, the transistor delay and power dissipation significantly reduced; however, a negative impact on the interconnect performance was realized. The reduction in the cross-sectional area of copper (Cu) interconnects resulted in higher resistivity under the effects of enhanced grain and surface scattering. Moreover, with smaller interconnect dimensions and higher operating frequency, the performance of Cu interconnects is gradually being limited by the electromigration effect, stability, operational bandwidth, and crosstalk. This trend is forcing researchers to find an alternative solution for high-speed very-large-scale integration (VLSI) interconnects.

Improved crosstalk noise modeling of MWCNT interconnects using FDTD technique

This paper presents a crosstalk noise model of CMOS gate-driven coupled multi-walled carbon nanotube (MWCNT) interconnects based on finite-difference time-domain (FDTD) technique. The analysis is based on the transmission line model of MWCNT interconnect and modified alpha power law model of CMOS driver. It is observed that the results of proposed model closely match with that of HSPICE simulations and at the same time the model is more time efficient than the HSPICE. Moreover, it is observed that the conventional models are not useful for accurate estimation of crosstalk induced performance parameters. Crosstalk noise model is presented for CMOS-gate driven MWCNT interconnects using FDTD.CMOS driver is modeled by modified alpha power law model.The proposed model is validated with industry standard HSPICE simulations.The average error while estimating the noise peak voltage is less than 2%.The proposed model can be incorporated in CAD simulation tools.

Carbon Nanotube Based 3-D Interconnects - A Reality or a Distant Dream

A 3D IC is a chip having multiple tiers of stacked dies. The vertically stacked dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development of a reliable 3D integrated system is largely dependent on the choice of filler material used in the TSV. Although, several researchers and fabrication houses have demonstrated the usage of copper as filler material, but, over the time it would suffer due to the rapid increase in resistivity under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly diffusive barrier layer. However, these limitations can be overcome by CNTs that exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. Moreover, a bundle of CNT conducts current parallely that drastically reduces the resistive parasitic and thereby propagation delay. Thus, bundled CNTs can be predicted as one of the potential candidates for future high-speed TSVs. However, the CNT growth temperature is greater than 600?A 3D IC is a chip having multiple tiers of stacked dies. The vertically stacked dies are electrically connected through 3D/vertical interconnects or popularly known as through-silicon-vias (TSVs). Development of a reliable 3D integrated system is largely dependent on the choice of filler material used in the TSV. Although, several researchers and fabrication houses have demonstrated the usage of copper as filler material, but, over the time it would suffer due to the rapid increase in resistivity under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of a highly diffusive barrier layer. However, these limitations can be overcome by CNTs that exhibit higher mechanical and thermal stability, higher conductivity and larger current carrying capability. Moreover, a bundle of CNT conducts current parallely that drastically reduces the resistive parasitic and thereby propagation delay. Thus, bundled CNTs can be predicted as one of the potential candidates for future high-speed TSVs. However, the CNT growth temperature is greater than 600°C that is unfortunately incompatible with CMOS devices and many other temperature-sensitive materials, therefore, the manufacturing of CNTs largely depends on the success of fabrication houses.C that is unfortunately incompatible with CMOS devices and many other temperature-sensitive materials, therefore, the manufacturing of CNTs largely depends on the success of fabrication houses.

Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect

In this paper, a more realistic analytical model for randomly distributed mixed carbon nanotube (CNT) bundle (MCB) is presented for the analysis of crosstalk induced delay. Several researchers have proposed analytical models for interconnects based on single-walled CNT (SWCNT), multi-walled CNT (MWCNT) bundle and most interestingly, spatially arranged mixed CNTs. Although, bundled SWCNTs and MWCNTs are easily realizable, but, practically it is almost impossible to fabricate a MCB with precise arrangements of SWCNTs and MWCNTs. Motivated by these facts, this paper presents a corner placement algorithm for randomly distributed SWCNTs and MWCNTs of different diameters in a MCB. The performance of MCB is compared with that of conventional bundled SWCNT and bundled MWCNT at different coupled interconnect lengths and spacing. Encouragingly, for a fixed cross-sectional area, the overall crosstalk induced delay of MCB reduces by 65.03% and 23.54% in comparison to the bundles having either SWCNTs or MWCNTs with smaller diameters, respectively. However, in contradiction to most of the previously reported results, bundled MWCNTs with larger diameters outperform the randomly distributed MCBs in terms of crosstalk performance.

Modeling of crosstalk effects in coupled MLGNR interconnects based on FDTD method

This paper presents an accurate and efficient model for the crosstalk analysis of coupled multilayer graphene nanoribbon (MLGNR) interconnects using finite-difference time-domain (FDTD) technique. The proposed model can be used for accurately estimating the voltage and current at any particular point on the interconnect line. The model is further extended to coupled-n interconnect lines with a low computational cost. Crosstalk induced performance parameters are measured using the proposed model and validated by comparing it to the HSPICE simulations. It is observed that the average error in estimating the noise peak voltage and propagation delay is less than 2%.