Voddarahalli K. Nagesh

Precision flip-chip solder bump interconnects for optical packaging

Solder bump flip-chip technology is particularly well suited to the packaging of classes of devices, such as fine pitch light emitting diode (LED) array electrophotographic print heads, which place premiums on precision alignment, high electrical interconnect density, close die placement, and low cost. The manufacturing feasibility of such an array was investigated, with particular emphasis on the quality of surface tension induced self-alignment inherent in solder bump bonding. An array of surface emitting LED diode array chips was fabricated employing 75- mu m-diameter solder bumps on 156- mu m pitch. The chips were spaced 15 mu m edge-to-edge, face down, on a glass substrate patterned with thin-film metallization. Chip-to-substrate alignment errors in the X-Y plane were found to be under 1.5 mu m with a standard deviation of under 1.0 mu m, well below the 10-15- mu m error typical of the standard mechanical alignment method. Improvements in light output uniformity and a reduction in scattered light over arrays manufactured with conventional die placement and wire bonding were also observed. >

Interconnect technologies for the 90's

Mainframe computers have provided the major driving forces for performance oriented interconnect and packaging technologies in the past. Consumer electronic products have driven the low cost of the spectrum. In the 90s, workstations with demands both on performance and price, and high volume peripheral and portable products with demands on price, performance and portability will drive the technologies. Driving towards a common possible set of chip interconnect technologies that are compatible with different substrate technologies will help in meeting the needs of the different market segments. Migration from single chip packages to multichip modules will be limited to applications having compelling performance requirements; multichip modules will become pervasive if test/burn-in and standardization issues of vendor supplied bare chip ICs are addressed and prices are attractive. Paradigm for technology development and access will change-from vertical integration to partnerships and outsourcing.

Multi-chip packaging for high performance systems

Multichip module (MCM) substrate, component assembly, and cooling technologies have been developed and demonstrated on several vehicles that include a 4-Kbyte RAM module operating at above 100-MHz clock frequency. An optimum MCM may consist of a set of composite layers of a multi-layer thin film polyimide structure over a multilayer ceramic substrate with a high pin density. The MCM technology provides system designers with increased circuit packing density and a larger number of accessible circuits, which results in lower machine-cycle time and cycles per instruction, leading to higher system performance. Moreover, the MCM technology opens up options for circuit organization and system architecture and for further improvements in system performance.<<ETX>>