W.A.M. Van Noije

A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, data-precharged, and NMOS-like CMOS blocks. The composition rules, as well as the CMOS blocks, are described and discussed. The experimental results of the complete dual-modulus prescaler, implemented in a 0.8 /spl mu/m CMOS process, show a maximum 1.59 GHz operation rate at 5 V with 12.8 mW power consumption. They are compared with the results from other recent implementations showing that the proposed E-TSPC circuit can reach high speed with both smaller area and lower power consumption.

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 /spl mu/m CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution. >

A methodology for CMOS low noise amplifier design

An intuitive strategy for CMOS low noise amplifier (LNA) design, compromising noise and linearity performance optimization, is presented. Analytical expressions for noise factor and IM3 are derived. The gain and power dissipation are considered pre-fixed parameters for this approach. A 2.4 GHz LNA has been designed and simulated in a 0.35 /spl mu/m CMOS technology to validate the proposed methodology.

Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design

New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 /spl mu/m CMOS process is fully depicted. This prescaler, according to simulations, reaches a maximum 2.19-GHz operation rate at 5 V with a 46 mW power consumption. This new approach is also compared with a previous design (implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate) and with other recently published circuits.

Precise final state determination of mismatched CMOS latches

The effect on the metastability of mismatched FET parameters and load capacitances of CMOS latch/flip-flop is analyzed. Theoretical analysis based on small signal devices are provided. From this study we show that the final state depends on both initial voltages and latch mismatches. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semi-planes. This straight line (the metastable line) determines precisely the final latch state, and gives a very good insight about the mismatches which exist in the latch. Several SPICE simulation results are shown for matched/mismatched flip-flops. They agree well with the theoretical ones. >

Metastability behavior of mismatched CMOS flip-flops using state diagram analysis

The effect on the metastability of the mismatch of FET parameters and load capacitances in a CMOS latch/flip-flop is analyzed. A novel method using state diagrams is proposed. On the state diagrams obtained by transient analysis of the latch, a straight line can be approximately drawn that defines two semiplanes, which precisely determine the latch final state. SPICE simulation results are shown for matched/mismatched flip-flops.

E-TSPC: Extended True Single-Phase­ Clock CMOS circuit technique

The Extended True Single-Phase-Clock (E-TSPC), an extension of the TSPC CMOS circuit technique, is proposed and analysed. This technique consists of a set of composition rules to build CMOS single-phase circuits. The composition rules are provided to avoid race problems and to preserve data during the holding phases. The used CMOS blocks are the conventional static CMOS logic, n/p dynamic logic, n/p latch, data precharged, and the new N-MOS like blocks. Design results show that the E-TSPC can achieve 70% speed improvements, comparing with conventional TSPC techniques, and large power and area savings. A complete dual-modulus prescaler (divide-by-128/129) was implemented in a 0.8µm CMOS process, and a 1.61GHz rate was achieved with a 14.2mW power consumption.

A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology

The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.

A CMOS implementation of the sine-circle map

A fully integrated CMOS implementation of an integrated-circuit relaxation oscillator neuron, IRON, is proposed. The circuit was designed using a 0.35 /spl mu/m technology. Simulation results show that the circuit is capable of generating bifurcation diagrams of the sine-circle map, while drawing only 4.8 /spl mu/A at 3.3 V power supply, with a 8.23 MHz sine-wave input signal. The total area occupied by the cell was 40 /spl mu/m /spl times/ 40 /spl mu/m.

SAMPA chip: a new ASIC for the ALICE TPC and MCH upgrades

This paper presents the SAMPA, an ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chambers (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and includes 32 channels, with selectable input polarity, and five possible combinations of shaping time and sensitivity. Each channel comprises a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC, followed by a Digital Signal Processor. A prototype in a multi project run was submitted to evaluate the performance of each of these blocks. The experimental results of the tests on these building blocks are presented, showing a substantial agreement with requirements.