W.C. Chien

Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material

Attempts to improve the retention so far must sacrifice switching speed. This work explores new phase change material based on pseudobinary GaSb-Ge system. The resulting new phase-change material has demonstrated fast switching speed of 80 ns, long endurance of 1G cycles and excellent data retention that survives 250°C-300 hrs. The 10 years-220°C data retention is the best ever reported. It is also the fastest material that can pass the solder bonding criteria for embedded automotive applications.

A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application

A new phase change material that provides fast SET speed, high cycling endurance, and large resistance window suitable for MLC SCM is investigated. Thorough understanding of the factors that affect the resistance distribution taught us to avoid operating near the melting temperature of the phase change material. By exploiting the self-converging property of low current SET operation we have designed a novel write scheme that provides fast and accurate MLC programming. High performance and high reliability 2-bits/cell MLC is demonstrated on a 512Mb test chip.

Reliability study of a 128Mb phase change memory chip implemented with doped Ga-Sb-Ge with extraordinary thermal stability

Doped Ga-Sb-Ge showed good thermal stability and fast switching speed. In this work, we present the results of a comprehensive reliability study for the relationship between cycling endurance and thermal stability on a 128Mb chip using modified doped Ga-Sb-Ge material. The chip exhibited good cycling endurance > 100K cycles, and there was no fail bits after soldering test. Furthermore, the chip showed no issue for 100K cycles after 260°C baking for 1000 seconds. In terms of the data retention, it was estimated that the PCM could retain data for 10 years at 215°C after 1K pre-cycles, 210°C after 10K pre-cycles, and 205°C after 100K pre-cycles. The PCM is suitable for applications requiring high thermal stability and cycling endurance.

A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multi-Level-Cell Performances

Inherent cell variation of phase change memory is difficult to control by material or device engineering alone. We previously reported R-I curve shift detection scheme as a good method for monitoring PCM cell characteristics. This paper extends that concept and proposes a Stress-trim procedure to tighten R-I characteristics for PCM MLC operation. By leveraging the right-shift phenomena of PCM R-I curves, we demonstrated that Stress-trim can effectively reduce cell variation to improve MLC performance. A MLC program current amplitude range reduction of 40% and MLC time to failure extension of nearly 150X are achieved.

A novel cross point one-resistor (0T1R) conductive bridge random access memory (CBRAM) with ultra low set/reset operation current

Using the dual Vth characteristics of a multi-layer SiO2/SiO2/Cu-GST conducting bridge (CB) structure we can construct a one-resistor cell without an access device (0T1R). Like 1T Flash memory the Vth is used to store the logic state thus leaving all devices always at high resistance state and a separate isolation device is not needed. The Vth of the cell is determined by the presence of CB in the SiO2 layer only. The CB in the SiO2 is present only temporarily during reading, and is spontaneously dissolved afterward. This spontaneous rupture of the filament in the SiO2 layer greatly reduces the switching current as well as reducing the read disturb. The mechanism for the spontaneous rupture phenomenon is investigated.

A Double-Data- Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications

For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.

A novel low power phase change memory using inter-granular switching

We propose and demonstrate a new low power phase change memory using a novel 3D network of crystallites with phase change confined to only at grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalcogenide glass is amorphized or crystallized for high or low resistance, we propose a multi-grained structure where we only induce phase change in the inter-grain regions. This not only drastically reduces the phase change volume but also improves the thermal efficiency of the cell. 3D simulation is used to understand the local heating effect. To create the multi-grained structure we have carefully studied the Ge/Sb/Te composition, the doping material and concentration and PVD deposition conditions. Consequently, the switching current can be reduced to 20uA. Furthermore, localizing the heating also reduces thermal disturbance to neighboring cells thus provides excellent pitch scalability.

Towards the integration of both ROM and RAM functions phase change memory cells on a single die for system-on-chip (SOC) applications

We discovered that by changing the dielectric capping layer above the phase change memory element we can change the SET speed and data retention of the memory. This allows us, for the first time, to integrate memories of different functions on the same chip with simple processes. By using a low temperature silicon nitride capping material we can get fast SET speed down to 20ns. With a high temperature silicon nitride capping material, on the other hand, data retention is increased to > 400 years at 85°C. Based on these discoveries, we propose a unified embedded memory solution which provides both ROM and RAM functions in a single chip for SOC applications.